From 6d1fdb34105a6ed894ce0aba85b9fb2eb3cf9d33 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 21 Jun 2017 14:44:13 +0200 Subject: AMD fam10: Link southbridge/amd/rs780/early_setup.c MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Removes rs780_before_pci_init() since it was a no-op anyway. Removes get_nb_rev() since this function is provided via a macro in the header. This Makes a lot of function non-static since the header has prototypes for these. Change-Id: I8933516771d959583bbd59a5c1beee3e30a7004f Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/20297 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/amd/bimini_fam10/romstage.c | 3 +-- src/mainboard/amd/mahogany/romstage.c | 3 +-- src/mainboard/amd/mahogany_fam10/romstage.c | 3 +-- src/mainboard/amd/tilapia_fam10/romstage.c | 3 +-- 4 files changed, 4 insertions(+), 8 deletions(-) (limited to 'src/mainboard/amd') diff --git a/src/mainboard/amd/bimini_fam10/romstage.c b/src/mainboard/amd/bimini_fam10/romstage.c index 1ca1d81b26..0c26416e75 100644 --- a/src/mainboard/amd/bimini_fam10/romstage.c +++ b/src/mainboard/amd/bimini_fam10/romstage.c @@ -41,7 +41,7 @@ #include #include #include -#include "southbridge/amd/rs780/early_setup.c" +#include #include "southbridge/amd/sb800/early_setup.c" #include @@ -200,7 +200,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) amdmct_cbmem_store_info(sysinfo); - rs780_before_pci_init(); sb800_before_pci_init(); post_code(0x42); diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 7cc45bf36e..979904a06f 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -47,7 +47,7 @@ int spd_read_byte(u32 device, u32 address) return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include "southbridge/amd/rs780/early_setup.c" +#include #include #include "northbridge/amd/amdk8/incoherent_ht.c" #include "lib/generic_sdram.c" @@ -142,6 +142,5 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr); sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo); - rs780_before_pci_init(); sb7xx_51xx_before_pci_init(); } diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index d292205a49..e5766c8ae9 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -46,7 +46,7 @@ #include #include #include -#include "southbridge/amd/rs780/early_setup.c" +#include #include #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) @@ -216,7 +216,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // die("After MCT init before CAR disabled."); - rs780_before_pci_init(); sb7xx_51xx_before_pci_init(); post_code(0x42); diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index e7e1e2fa15..89d170cb5a 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -45,7 +45,7 @@ #include #include #include -#include "southbridge/amd/rs780/early_setup.c" +#include #include "resourcemap.c" #include "cpu/amd/quadcore/quadcore.c" @@ -201,7 +201,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) amdmct_cbmem_store_info(sysinfo); - rs780_before_pci_init(); sb7xx_51xx_before_pci_init(); post_code(0x42); -- cgit v1.2.3