From 4e3658fd57bd39acf66cd8061b22c3533068feab Mon Sep 17 00:00:00 2001
From: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Date: Mon, 3 May 2021 06:52:53 -0700
Subject: mb/amd/majolica: Enable S0i3 by default

Set s0ix_enable to true.

BUG=b:178728116
TEST=Cold boot and perform a cycle of S0i3.

Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com>
Change-Id: I808e78f41509cb03821513b5b63cc8856c891d8c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52857
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
---
 src/mainboard/amd/majolica/devicetree.cb | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'src/mainboard/amd')

diff --git a/src/mainboard/amd/majolica/devicetree.cb b/src/mainboard/amd/majolica/devicetree.cb
index fec764e0a5..502ae251e0 100644
--- a/src/mainboard/amd/majolica/devicetree.cb
+++ b/src/mainboard/amd/majolica/devicetree.cb
@@ -14,6 +14,8 @@ chip soc/amd/cezanne
 		.flash_ch_en = 0,
 	}"
 
+	register "s0ix_enable" = "true"
+
 	device domain 0 on
 		device ref gpp_gfx_bridge_0 on end # MXM
 		device ref gpp_bridge_0 on end # NVMe
-- 
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