From 0fc69141e523ef3dba5ce840dea68de40b0ec785 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 8 May 2024 21:44:46 +0200 Subject: vc/amd/opensil: introduce common mpio/chip.h header file The chip drivers in the devicetree use the path where the corresponding chip.h file resides both to include this chip.h file in the static.c generated by util/sconfig from the devicetree and also for the names of the chip config and chip ops struct. To be able to build a SoC using either the MPIO chip driver from the openSIL stub or from the actual openSIL glue code without needing different devicetree files for the different cases, introduce a common MPIO chip.h file that then includes the correct MPIO header file. The chip config and ops structures also need to be renamed to take this change into account. Thanks to Matt for pointing out how to make the path to the actual MPIO chip.h file configurable via a Kconfig setting. This allows overriding this path from site-local without the need to have any reference to site-local in the upstream code. Signed-off-by: Felix Held Change-Id: Iead97d1727569ec0d23a2b9c4fd96daff4bebcf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/82262 Reviewed-by: Varshit Pandya Reviewed-by: Martin L Roth Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- src/mainboard/amd/onyx_poc/devicetree.cb | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) (limited to 'src/mainboard/amd') diff --git a/src/mainboard/amd/onyx_poc/devicetree.cb b/src/mainboard/amd/onyx_poc/devicetree.cb index c1b2f5c28c..f3c0be4561 100644 --- a/src/mainboard/amd/onyx_poc/devicetree.cb +++ b/src/mainboard/amd/onyx_poc/devicetree.cb @@ -55,7 +55,7 @@ chip soc/amd/genoa_poc device domain 0 on device ref iommu_0 on end device ref rcec_0 on end - chip vendorcode/amd/opensil/genoa_poc/mpio # P2 + chip vendorcode/amd/opensil/chip/mpio # P2 register "type" = "IFTYPE_PCIE" register "start_lane" = "48" register "end_lane" = "63" @@ -63,7 +63,7 @@ chip soc/amd/genoa_poc register "aspm" = "L1" device ref gpp_bridge_0_0_a on end end - chip vendorcode/amd/opensil/genoa_poc/mpio # G2 + chip vendorcode/amd/opensil/chip/mpio # G2 register "type" = "IFTYPE_PCIE" register "start_lane" = "112" register "end_lane" = "127" @@ -72,7 +72,7 @@ chip soc/amd/genoa_poc register "hotplug" = "ServerExpress" device ref gpp_bridge_0_0_b on end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/chip/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "128" register "end_lane" = "131" @@ -93,7 +93,7 @@ chip soc/amd/genoa_poc device domain 1 on device ref iommu_1 on end device ref rcec_1 on end - chip vendorcode/amd/opensil/genoa_poc/mpio # P3 + chip vendorcode/amd/opensil/chip/mpio # P3 register "type" = "IFTYPE_PCIE" register "start_lane" = "16" register "end_lane" = "31" @@ -101,7 +101,7 @@ chip soc/amd/genoa_poc register "aspm" = "L1" device ref gpp_bridge_1_0_a on end end - chip vendorcode/amd/opensil/genoa_poc/mpio # G3 + chip vendorcode/amd/opensil/chip/mpio # G3 register "type" = "IFTYPE_PCIE" register "start_lane" = "80" register "end_lane" = "95" @@ -114,7 +114,7 @@ chip soc/amd/genoa_poc device domain 2 on device ref iommu_2 on end device ref rcec_2 on end - chip vendorcode/amd/opensil/genoa_poc/mpio # P1 + chip vendorcode/amd/opensil/chip/mpio # P1 register "type" = "IFTYPE_PCIE" register "start_lane" = "32" register "end_lane" = "47" @@ -123,7 +123,7 @@ chip soc/amd/genoa_poc register "hotplug" = "ServerExpress" device ref gpp_bridge_2_0_a on end end - chip vendorcode/amd/opensil/genoa_poc/mpio # G1 + chip vendorcode/amd/opensil/chip/mpio # G1 register "type" = "IFTYPE_PCIE" register "start_lane" = "64" register "end_lane" = "79" @@ -137,7 +137,7 @@ chip soc/amd/genoa_poc device domain 3 on device ref iommu_3 on end device ref rcec_3 on end - chip vendorcode/amd/opensil/genoa_poc/mpio # P0 + chip vendorcode/amd/opensil/chip/mpio # P0 register "type" = "IFTYPE_PCIE" register "start_lane" = "0" register "end_lane" = "15" @@ -145,7 +145,7 @@ chip soc/amd/genoa_poc register "aspm" = "L1" device ref gpp_bridge_3_0_a on end end - chip vendorcode/amd/opensil/genoa_poc/mpio # G0 + chip vendorcode/amd/opensil/chip/mpio # G0 register "type" = "IFTYPE_PCIE" register "start_lane" = "96" register "end_lane" = "111" @@ -153,7 +153,7 @@ chip soc/amd/genoa_poc register "aspm" = "L1" device ref gpp_bridge_3_0_b on end end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/chip/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "132" register "end_lane" = "133" @@ -161,7 +161,7 @@ chip soc/amd/genoa_poc register "aspm" = "L1" device ref gpp_bridge_3_0_c on end # WAFL end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/chip/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "134" register "end_lane" = "134" @@ -170,7 +170,7 @@ chip soc/amd/genoa_poc register "bmc" = "1" device ref gpp_bridge_3_1_c on end # BMC end - chip vendorcode/amd/opensil/genoa_poc/mpio + chip vendorcode/amd/opensil/chip/mpio register "type" = "IFTYPE_PCIE" register "start_lane" = "135" register "end_lane" = "135" -- cgit v1.2.3