From 75a3d1fb7c31bc5bd287bf6579ff70c5da9275a7 Mon Sep 17 00:00:00 2001 From: Damien Zammit Date: Mon, 28 Nov 2016 00:29:10 +1100 Subject: amdfam10: Perform major include ".c" cleanup Previously, all romstages for this northbridge family would compile via 1 single C file with everything included into the romstage.c file (!) This patch separates the build into separate .o modules and links them accordingly. Currently compiles and links all fam10 roms without breaking other roms. Both DDR2 and DDR3 have been completed TESTED on REACTS: passes all boot tests for 2 boards ASUS KGPE-D16 ASUS KFSN4-DRE Some extra changes were required to make it compile otherwise there were unused functions in included "c" files. This is because I needed to exchange CIMX for the native southbridge routines. See in particular: advansus/a785e-i asus/m5a88-v avalue/eax-785e A followup patch may be required to fix the above boards. See FIXME, XXX tags Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426 Signed-off-by: Damien Zammit Reviewed-on: https://review.coreboot.org/17625 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand Reviewed-by: Timothy Pearson --- src/mainboard/amd/tilapia_fam10/romstage.c | 35 +++++++++++++++--------------- 1 file changed, 17 insertions(+), 18 deletions(-) (limited to 'src/mainboard/amd/tilapia_fam10') diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c index c68fcccced..022e91de19 100644 --- a/src/mainboard/amd/tilapia_fam10/romstage.c +++ b/src/mainboard/amd/tilapia_fam10/romstage.c @@ -29,41 +29,40 @@ #include #include #include -#include -#include #include #include -#include "northbridge/amd/amdfam10/reset_test.c" #include #include #include #include #include -#include "northbridge/amd/amdfam10/setup_resource_map.c" -#include "southbridge/amd/rs780/early_setup.c" +#include #include #include -#include "northbridge/amd/amdfam10/debug.c" +#include +#include +#include +#include +#include +#include +#include "southbridge/amd/rs780/early_setup.c" + +#include "resourcemap.c" +#include "cpu/amd/quadcore/quadcore.c" #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +extern struct sys_info sysinfo_car; + +void activate_spd_rom(const struct mem_controller *ctrl) { } -static int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } -#include -#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c" -#include "northbridge/amd/amdfam10/pci.c" -#include "resourcemap.c" -#include "cpu/amd/quadcore/quadcore.c" -#include - -#include "cpu/amd/family_10h-family_15h/init_cpus.c" -#include "northbridge/amd/amdfam10/early_ht.c" -#include void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -- cgit v1.2.3