From 657d68bddc030e38bc19eb4eef07f59b5e5258e4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 3 Dec 2019 12:36:09 +0200 Subject: AGESA,binaryPI: Move PORT80 selection to C bootblock MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Because the function is implemented in C, post_code() calls from cache_as_ram.S and other early assembly entry files may not currently work for cold boots. Assembly implementation needs to follow one day. This effectively removes PORT80 routing from boards with ROMCC_BOOTBLOCK. Change-Id: I71aa94b33bd6f65e243724810472a440e98e0750 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/37451 Tested-by: build bot (Jenkins) Reviewed-by: Michał Żygowski --- src/mainboard/amd/thatcher/Kconfig | 1 + src/mainboard/amd/thatcher/romstage.c | 1 - 2 files changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/amd/thatcher') diff --git a/src/mainboard/amd/thatcher/Kconfig b/src/mainboard/amd/thatcher/Kconfig index e11d0ea1d9..2c0939c84e 100644 --- a/src/mainboard/amd/thatcher/Kconfig +++ b/src/mainboard/amd/thatcher/Kconfig @@ -21,6 +21,7 @@ config BOARD_SPECIFIC_OPTIONS select CPU_AMD_AGESA_FAMILY15_TN select NORTHBRIDGE_AMD_AGESA_FAMILY15_TN select SOUTHBRIDGE_AMD_AGESA_HUDSON + select DEFAULT_POST_ON_LPC select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 1d89e4d6d1..5678021f8b 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -31,7 +31,6 @@ void board_BeforeAgesa(struct sysinfo *cb) /* Set LPC decode enables. */ dev = PCI_DEV(0, 0x14, 3); - hudson_lpc_port80(); byte = pci_read_config8(dev, 0x48); byte |= 3; /* 2e, 2f */ -- cgit v1.2.3