From 59e03342076ea79cb7c0ed2fdbd199947c8c5212 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sun, 20 Nov 2016 11:03:13 +0200 Subject: AGESA: Switch to MMCONF_SUPPORT_DEFAULT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Vendorcode always does PCI MMCONF access once it is enabled via MSR. In coreboot proper, we don't give opportunity to make pci_read/write calls before PCI MMCONF is enabled via MSR. This happens early in romstage amd_initmmio() for all cores. Change-Id: If31bc0a67b480bcc1d955632f413f5cdeec51a54 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/17533 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/amd/thatcher/romstage.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/amd/thatcher') diff --git a/src/mainboard/amd/thatcher/romstage.c b/src/mainboard/amd/thatcher/romstage.c index 4c9c8fa1b3..147f31acce 100644 --- a/src/mainboard/amd/thatcher/romstage.c +++ b/src/mainboard/amd/thatcher/romstage.c @@ -43,6 +43,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) u8 byte; pci_devfn_t dev; + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); /* Set LPC decode enables. */ -- cgit v1.2.3