From 09574d5c3c920d2959336a25064f9651df39e30e Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 14 Jan 2013 15:46:38 -0700 Subject: Fix high dword of MTRR mask set with CONFIG_CPU_ADDR_BITS Bits were being shifted off the end of the mask accidentally. This results in all masks being 32 bits wide instead of 48. Change-Id: I5f4d1b6a323df1aa4568ff4491f82447b8a2f839 Signed-off-by: Martin Roth Reviewed-on: http://review.coreboot.org/2146 Tested-by: build bot (Jenkins) Reviewed-by: Zheng Bao Reviewed-by: Marc Jones Reviewed-by: Paul Menzel --- src/mainboard/amd/thatcher/agesawrapper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/amd/thatcher') diff --git a/src/mainboard/amd/thatcher/agesawrapper.c b/src/mainboard/amd/thatcher/agesawrapper.c index 7a3616b480..aaff34b2ca 100644 --- a/src/mainboard/amd/thatcher/agesawrapper.c +++ b/src/mainboard/amd/thatcher/agesawrapper.c @@ -166,7 +166,7 @@ agesawrapper_amdinitmmio ( /* Set ROM cache onto WP to decrease post time */ MsrReg = (0x0100000000ull - CONFIG_ROM_SIZE) | 5ull; LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); - MsrReg = ((1UL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; + MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CONFIG_ROM_SIZE) | 0x800ull; LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); Status = AGESA_SUCCESS; -- cgit v1.2.3