From aedcc10ad30f3fcc1397035876672d235418393f Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 21 Jul 2014 08:07:19 +0200 Subject: src/mainboard: Remove trailing whitespace Change-Id: I14a9dc99acb5d5365a3d7e99a3964120bb611b05 Signed-off-by: Elyes HAOUAS Reviewed-on: http://review.coreboot.org/6308 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/amd/serengeti_cheetah_fam10/romstage.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'src/mainboard/amd/serengeti_cheetah_fam10') diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c index 09b86bb9e2..6388b42e94 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah_fam10/romstage.c @@ -64,7 +64,7 @@ static void activate_spd_rom(const struct mem_controller *ctrl) int ret,i; u8 device = ctrl->spd_switch_addr; - printk(BIOS_DEBUG, "switch i2c to : %02x for node %02x \n", device, ctrl->node_id); + printk(BIOS_DEBUG, "switch i2c to : %02x for node %02x\n", device, ctrl->node_id); /* the very first write always get COL_STS=1 and ABRT_STS=1, so try another time*/ i=2; @@ -215,10 +215,10 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) // Load MPB val = cpuid_eax(1); - printk(BIOS_DEBUG, "BSP Family_Model: %08x \n", val); + printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val); printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1); - printk(BIOS_DEBUG, "bsp_apicid = %02x \n", bsp_apicid); - printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx \n", cpu_init_detectedx); + printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid); + printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx); /* Setup sysinfo defaults */ set_sysinfo_in_ram(0); @@ -260,7 +260,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) #if CONFIG_SET_FIDVID msr = rdmsr(0xc0010071); - printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); /* FIXME: The sb fid change may survive the warm reset and only need to be done once.*/ @@ -278,7 +278,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) /* show final fid and vid */ msr=rdmsr(0xc0010071); - printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo); + printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo); #endif /* Reset for HT, FIDVID, PLL and errata changes to take affect. */ -- cgit v1.2.3