From 99c45dee0ae62254be36a312d67764784450b564 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sun, 15 Oct 2017 14:16:37 -0600 Subject: AMD GX2 boards & chips: Remove - using LATE_CBMEM_INIT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit All boards and chips that are still using LATE_CBMEM_INIT are being removed as previously discussed. If these boards and chips are updated to not use LATE_CBMEM_INIT, they can be restored to the active codebase from the 4.7 branch. chips: cpu/amd/geode_gx2 northbridge/amd/gx2 southbridge/amd/cs5535 Mainboards: mainboard/amd/rumba mainboard/lippert/frontrunner mainboard/wyse/s50 Change-Id: I81c130f53bbfa001edbfdb7a878ef115757f620c Signed-off-by: Martin Roth Reviewed-on: https://review.coreboot.org/22025 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki --- src/mainboard/amd/rumba/devicetree.cb | 20 -------------------- 1 file changed, 20 deletions(-) delete mode 100644 src/mainboard/amd/rumba/devicetree.cb (limited to 'src/mainboard/amd/rumba/devicetree.cb') diff --git a/src/mainboard/amd/rumba/devicetree.cb b/src/mainboard/amd/rumba/devicetree.cb deleted file mode 100644 index d48035521c..0000000000 --- a/src/mainboard/amd/rumba/devicetree.cb +++ /dev/null @@ -1,20 +0,0 @@ -chip northbridge/amd/gx2 - device cpu_cluster 0 on - chip cpu/amd/geode_gx2 - device lapic 0 on end - end - end - device domain 0 on - device pci 1.0 on end - device pci 1.1 on end - chip southbridge/amd/cs5536 - register "lpc_serirq_enable" = "0x80" # enabled with default timing - device pci d.0 on end # Realtek 8139 LAN - device pci f.0 on end # ISA Bridge - device pci f.2 on end # IDE Controller - device pci f.3 on end # Audio - device pci f.4 on end # OHCI - device pci f.5 on end # EHCI - end - end -end -- cgit v1.2.3