From 888df97971271655a2b3cacf96d509dadf15fd85 Mon Sep 17 00:00:00 2001
From: Stefan Reinauer <stepan@openbios.org>
Date: Fri, 24 Oct 2003 14:45:21 +0000
Subject: merge latest quartet changes

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1231 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
---
 src/mainboard/amd/quartet/Config.lb | 71 +++++++++++++++++++++----------------
 1 file changed, 40 insertions(+), 31 deletions(-)

(limited to 'src/mainboard/amd/quartet/Config.lb')

diff --git a/src/mainboard/amd/quartet/Config.lb b/src/mainboard/amd/quartet/Config.lb
index 90f56355f6..cbcb340fe2 100644
--- a/src/mainboard/amd/quartet/Config.lb
+++ b/src/mainboard/amd/quartet/Config.lb
@@ -15,6 +15,9 @@ uses _ROMBASE
 uses XIP_ROM_SIZE
 uses XIP_ROM_BASE
 
+## ROM_SIZE is the size of boot ROM that this board will use.
+default ROM_SIZE 524288
+
 ###
 ### Build options
 ###
@@ -68,9 +71,6 @@ option MAINBOARD_VENDOR="AMD"
 ### LinuxBIOS layout values
 ###
 
-## ROM_SIZE is the size of boot ROM that this board will use.
-option ROM_SIZE = 524288
-
 ## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
 option ROM_IMAGE_SIZE = 65536
 
@@ -159,7 +159,7 @@ makerule ./auto.E
 end
 makerule ./auto.inc 
 	depends "./auto.E ./romcc"
-	action	"./romcc -mcpu=k8  -O ./auto.E > auto.inc"
+	action	"./romcc -mcpu=k8 -O2 ./auto.E > auto.inc"
 end
 
 ##
@@ -229,32 +229,30 @@ northbridge amd/amdk8 "mc0"
 	pci 0:18.1
 	pci 0:18.2
 	pci 0:18.3
-	southbridge amd/amd8131 "amd8131"
-		pci 0:0.0
-		pci 0:0.1
-		pci 0:1.0
-		pci 0:1.1
-	end
-	southbridge amd/amd8111 "amd8111"
-		pci 0:0.0
-		pci 0:1.0
-		pci 0:1.1
-		pci 0:1.2
-		pci 0:1.3
-		pci 0:1.5
-		pci 0:1.6
-		superio NSC/pc87360
-			pnp 1:2e.0
-			pnp 1:2e.1
-			pnp 1:2e.2
-			pnp 1:2e.3
-			pnp 1:2e.4
-			pnp 1:2e.5
-			pnp 1:2e.6
-			pnp 1:2e.7
-			pnp 1:2e.8
-			pnp 1:2e.9
-			pnp 1:2e.a
+	southbridge amd/amd8111 "amd8111" link 2
+		pci 0:0.0 on
+		pci 0:1.0 on
+		pci 0:1.1 on
+		pci 0:1.2 on
+		pci 0:1.3 on
+		pci 0:1.5 on
+		pci 0:1.6 on
+		pci 1:0.0 on
+		pci 1:0.1 on
+		pci 1:0.2 on
+		pci 1:1.0 on
+		superio NSC/pc87360 link 1
+			pnp 2e.0
+			pnp 2e.1
+			pnp 2e.2
+			pnp 2e.3
+			pnp 2e.4
+			pnp 2e.5
+			pnp 2e.6
+			pnp 2e.7
+			pnp 2e.8
+			pnp 2e.9
+			pnp 2e.a
 			register "com1" = "{1, 0, 0x3f8, 4}"
 			register "lpt" = "{1}"
 		end
@@ -268,6 +266,18 @@ northbridge amd/amdk8 "mc1"
 	pci 0:19.1
 	pci 0:19.2
 	pci 0:19.3
+	southbridge amd/amd8131 "amd8131" link 1
+		pci 0:0.0
+		pci 0:0.1
+		pci 0:1.0
+		pci 0:1.1
+	end
+	southbridge amd/amd8131 "amd8131" link 1
+		pci 0:0.0
+		pci 0:0.1
+		pci 0:1.0
+		pci 0:1.1
+	end
 end
 
 northbridge amd/amdk8 "mc2"
@@ -289,7 +299,6 @@ northbridge amd/amdk8 "mc3"
 end
 
 cpu k8 "cpu0"
-	register "up" = "{ .chip = &amd8131, .ht_width=16, .ht_speed=600 }"
 end
 
 cpu k8 "cpu1" 
-- 
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