From 2b34db8d1de2d63ffa829fe03db0ce2aaba40233 Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Sat, 28 Feb 2009 20:10:20 +0000 Subject: coreboot-v2: drop this ugly historic union name in v2 that was dropped in v3 a long time ago. This will make it easier to port v2 boards forward to v3 at some point (and other things) Signed-off-by: Stefan Reinauer Acked-by: Carl-Daniel Hailfinger git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3964 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/amd/pistachio/mainboard.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'src/mainboard/amd/pistachio/mainboard.c') diff --git a/src/mainboard/amd/pistachio/mainboard.c b/src/mainboard/amd/pistachio/mainboard.c index 960c74954d..7651180127 100644 --- a/src/mainboard/amd/pistachio/mainboard.c +++ b/src/mainboard/amd/pistachio/mainboard.c @@ -169,26 +169,26 @@ static void set_thermal_config() sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0)); dword = pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary, - sm_dev->path.u.pci.devfn, 0x64); + sm_dev->path.pci.devfn, 0x64); dword |= 1 << 19; pci_cf8_conf1.write32(&pbus, sm_dev->bus->secondary, - sm_dev->path.u.pci.devfn, 0x64, dword); + sm_dev->path.pci.devfn, 0x64, dword); /* Enable Client Management Index/Data registers */ dword = pci_cf8_conf1.read32(&pbus, sm_dev->bus->secondary, - sm_dev->path.u.pci.devfn, 0x78); + sm_dev->path.pci.devfn, 0x78); dword |= 1 << 11; /* Cms_enable */ pci_cf8_conf1.write32(&pbus, sm_dev->bus->secondary, - sm_dev->path.u.pci.devfn, 0x78, dword); + sm_dev->path.pci.devfn, 0x78, dword); /* MiscfuncEnable */ byte = pci_cf8_conf1.read8(&pbus, sm_dev->bus->secondary, - sm_dev->path.u.pci.devfn, 0x41); + sm_dev->path.pci.devfn, 0x41); byte |= (1 << 5); pci_cf8_conf1.write8(&pbus, sm_dev->bus->secondary, - sm_dev->path.u.pci.devfn, 0x41, byte); + sm_dev->path.pci.devfn, 0x41, byte); /* set GPM5 as input */ /* set index register 0C50h to 13h (miscellaneous control) */ @@ -230,10 +230,10 @@ static void set_thermal_config() /* set GPIO 64 to input */ word = pci_cf8_conf1.read16(&pbus, sm_dev->bus->secondary, - sm_dev->path.u.pci.devfn, 0x56); + sm_dev->path.pci.devfn, 0x56); word |= 1 << 7; pci_cf8_conf1.write16(&pbus, sm_dev->bus->secondary, - sm_dev->path.u.pci.devfn, 0x56, word); + sm_dev->path.pci.devfn, 0x56, word); /* set GPIO 64 internal pull-up */ byte = pm2_ioread(0xf0); -- cgit v1.2.3