From 45f72ce60f41a655514c29698678cf3c1fb0c1a9 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sun, 24 Feb 2013 12:58:33 -0700 Subject: AMD Persimmon: Use SPD read code from F14 wrapper Changes: - Get rid of the persimmon mainboard specific code which has been moved into the wrapper as a platform generic function in change http://review.coreboot.org/#/c/2497/ AMD f14: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb - Add the ASF init that used to be in the SPD read code into mainboard_enable() Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: I5f017dbb8dee5a09ec19734a6069ff9b71a6ab50 Signed-off-by: Martin Roth Reviewed-on: http://review.coreboot.org/2500 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich Reviewed-by: Jens Rottmann Reviewed-by: Marc Jones --- src/mainboard/amd/persimmon/devicetree.cb | 7 +++++++ 1 file changed, 7 insertions(+) (limited to 'src/mainboard/amd/persimmon/devicetree.cb') diff --git a/src/mainboard/amd/persimmon/devicetree.cb b/src/mainboard/amd/persimmon/devicetree.cb index d108a11e5d..8b1acd5bb3 100644 --- a/src/mainboard/amd/persimmon/devicetree.cb +++ b/src/mainboard/amd/persimmon/devicetree.cb @@ -149,6 +149,13 @@ chip northbridge/amd/agesa/family14/root_complex device pci 18.5 on end device pci 18.6 on end device pci 18.7 on end + + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + { {0x00, 0x00}, {0x00, 0x00}, }, // socket 1 - Channel 0 & 1 - 8-bit SPD addresses + }" + end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family14/root_complex -- cgit v1.2.3