From 9a98fc9d1d40f5bd58e587f81cdb38a482a0a91f Mon Sep 17 00:00:00 2001 From: Felix Held Date: Thu, 22 Jul 2021 17:46:16 +0200 Subject: soc/amd/stoneyridge/fch: change sb prefix of sb_clk_output_48Mhz to fch Stoneyridge has an integrated FCH and no south bridge, so change the sb prefix to fch. Signed-off-by: Felix Held Change-Id: I5154ae1158f864d4a2aca55e6bcce6a742c6afe1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/56527 Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/mainboard/amd/padmelon/bootblock/bootblock.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/amd/padmelon') diff --git a/src/mainboard/amd/padmelon/bootblock/bootblock.c b/src/mainboard/amd/padmelon/bootblock/bootblock.c index 13e050d628..d8c462d17a 100644 --- a/src/mainboard/amd/padmelon/bootblock/bootblock.c +++ b/src/mainboard/amd/padmelon/bootblock/bootblock.c @@ -31,7 +31,7 @@ static void enable_serial(unsigned int base_port, unsigned int io_enable) void bootblock_mainboard_early_init(void) { - sb_clk_output_48Mhz(2); + fch_clk_output_48Mhz(2); /* * UARTs enabled by default at reset, just need RTS, CTS * and access to the IO address. -- cgit v1.2.3