From f0d62cefe855017a9e3f47aa3b0fc187ef8a5931 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 14 Oct 2022 17:48:22 +0200 Subject: mb/amd/padmelon: rename to pademelon This AMD reference board is called Pademelon and not Padmelon, so fix the name in coreboot. Also update the corresponding documentation. Signed-off-by: Felix Held Change-Id: Id1c7331f5f3c34dc7ec4bc5a1f5fe3d12d503474 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68426 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/amd/pademelon/gpio.c | 53 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 53 insertions(+) create mode 100644 src/mainboard/amd/pademelon/gpio.c (limited to 'src/mainboard/amd/pademelon/gpio.c') diff --git a/src/mainboard/amd/pademelon/gpio.c b/src/mainboard/amd/pademelon/gpio.c new file mode 100644 index 0000000000..0de2c0a190 --- /dev/null +++ b/src/mainboard/amd/pademelon/gpio.c @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include "gpio.h" + +/* + * As a rule of thumb, GPIO pins used by coreboot should be initialized at + * bootblock while GPIO pins used only by the OS should be initialized at + * ramstage. + */ +static const struct soc_amd_gpio gpio_set_stage_reset[] = { + /* GFX presence detect */ + PAD_GPI(GPIO_9, PULL_DOWN), + /* VDDP_VCTRL */ + PAD_GPO(GPIO_40, HIGH), + /* PC SPKR */ + PAD_NF(GPIO_91, SPKR, PULL_NONE), +}; + +static const struct soc_amd_gpio gpio_set_stage_ram[] = { +#if CONFIG(HAVE_ACPI_RESUME) + /* PCIE_WAKE - default, do not program */ + + /* DEVSLP1 */ + PAD_NF(GPIO_70, DEVSLP1, PULL_UP), + /* WLAND */ + PAD_WAKE(GPIO_137, PULL_UP, LEVEL_LOW, S3), +#else + /* PCIE_WAKE, SCI */ + PAD_NF_SCI(GPIO_2, WAKE_L, PULL_UP, EDGE_LOW), + /* DEVSLP1 - default as GPIO, do not program */ + + /* WLAND - default as GPIO, do not program */ + +#endif /* HAVE_ACPI_RESUME */ + /* BLINK - reselect GPIO OUTPUT HIGH to force BLINK */ + PAD_GPO(GPIO_11, HIGH), +}; + +const struct soc_amd_gpio *early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_reset); + return gpio_set_stage_reset; +} + +const struct soc_amd_gpio *gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_ram); + return gpio_set_stage_ram; +} -- cgit v1.2.3