From d123f8d8716811149ecdf7d51661d8cee6f48577 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 15 Dec 2023 10:57:30 +0100 Subject: soc/amd/genoa: rename to genoa_poc Even though this SoC is called 'Genoa', the openSIL implementation and the corresponding coreboot integration is only a proof of concept that isn't fully featured, has known limitations and bugs, and is not meant for or ready to being productized. Adding the proof of concept suffix to the name should point this out clearly enough so that no potential customer could infer that this might be a fully functional and supported implementation which it is not. Change-Id: Ia459b1e007dcfd8e8710c12e252b2f9a4ae19b72 Signed-off-by: Varshit Pandya Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/77894 Reviewed-by: Martin Roth Reviewed-by: Marshall Dawson Tested-by: build bot (Jenkins) --- src/mainboard/amd/onyx/devicetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'src/mainboard/amd/onyx/devicetree.cb') diff --git a/src/mainboard/amd/onyx/devicetree.cb b/src/mainboard/amd/onyx/devicetree.cb index d53da0ed1f..a18eff40da 100644 --- a/src/mainboard/amd/onyx/devicetree.cb +++ b/src/mainboard/amd/onyx/devicetree.cb @@ -1,4 +1,4 @@ -chip soc/amd/genoa +chip soc/amd/genoa_poc # USB configuration register "usb.xhci0_enable" = "1" -- cgit v1.2.3