From c666a916112aece345da57a0b4f3bafc43234ee7 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 13 Jul 2023 14:34:10 +0200 Subject: soc/amd/genoa: Enable eSPI early Signed-off-by: Arthur Heymans Change-Id: I4965eac4ec3d600b1e840affce4e5b4fa2ea4360 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76508 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held Reviewed-by: Martin Roth --- src/mainboard/amd/onyx/devicetree.cb | 13 +++++++++++++ 1 file changed, 13 insertions(+) (limited to 'src/mainboard/amd/onyx/devicetree.cb') diff --git a/src/mainboard/amd/onyx/devicetree.cb b/src/mainboard/amd/onyx/devicetree.cb index 5f447b2540..2b37b761fd 100644 --- a/src/mainboard/amd/onyx/devicetree.cb +++ b/src/mainboard/amd/onyx/devicetree.cb @@ -1,5 +1,18 @@ chip soc/amd/genoa + # eSPI configuration + register "common_config.espi_config" = "{ + .std_io_decode_bitmap = ESPI_DECODE_IO_0x80_EN, + .io_mode = ESPI_IO_MODE_SINGLE, + .op_freq_mhz = ESPI_OP_FREQ_33_MHZ, + .crc_check_enable = 1, + .alert_pin = ESPI_ALERT_PIN_PUSH_PULL, + .periph_ch_en = 0, + .vw_ch_en = 0, + .oob_ch_en = 0, + .flash_ch_en = 0, + }" + device domain 0 on end -- cgit v1.2.3