From 4c548919c617d7a19482c23156a7546f0e18164f Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 5 Apr 2023 19:57:44 +0200 Subject: vc/amd/fps/phoenix/platform_descriptors: drop logical-physical mapping For Phoenix the lane numbers in the DXIO descriptor match the ones in the schematic, so remove the corresponding text and the table from the comment on the fsp_dxio_descriptor struct. Since there's no logical to physical lane number remapping needed for the lanes in the Phoenix DXIO descriptors, drop the 'logical' from the start_logical_lane and end_logical_lane fields in the DXIO descriptor and rename those to start_lane and end_lane. Signed-off-by: Felix Held Change-Id: I94664fd9d3807370b73f9fae8645d444e5faf7b7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74223 Tested-by: build bot (Jenkins) Reviewed-by: Fred Reitberger Reviewed-by: Eric Lai --- src/mainboard/amd/mayan/port_descriptors.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) (limited to 'src/mainboard/amd/mayan') diff --git a/src/mainboard/amd/mayan/port_descriptors.c b/src/mainboard/amd/mayan/port_descriptors.c index 6654806c50..c2e267c7cc 100644 --- a/src/mainboard/amd/mayan/port_descriptors.c +++ b/src/mainboard/amd/mayan/port_descriptors.c @@ -13,8 +13,8 @@ static const fsp_dxio_descriptor mayan_dxio_descriptors[] = { // MXM .engine_type = PCIE_ENGINE, .port_present = true, - .start_logical_lane = 0, - .end_logical_lane = 3, + .start_lane = 0, + .end_lane = 3, .device_number = 1, .function_number = 1, .link_speed_capability = GEN_MAX, @@ -33,8 +33,8 @@ static const fsp_dxio_descriptor mayan_dxio_descriptors[] = { // M2 SSD0-NVME .engine_type = PCIE_ENGINE, .port_present = true, - .start_logical_lane = 16, - .end_logical_lane = 19, + .start_lane = 16, + .end_lane = 19, .device_number = 2, .function_number = 4, .link_speed_capability = GEN_MAX, @@ -53,8 +53,8 @@ static const fsp_dxio_descriptor mayan_dxio_descriptors[] = { // X1 .engine_type = PCIE_ENGINE, .port_present = true, - .start_logical_lane = 12, - .end_logical_lane = 12, + .start_lane = 12, + .end_lane = 12, .device_number = 1, .function_number = 3, .link_speed_capability = GEN_MAX, @@ -72,8 +72,8 @@ static const fsp_dxio_descriptor mayan_dxio_descriptors[] = { // DT .engine_type = PCIE_ENGINE, .port_present = true, - .start_logical_lane = 8, - .end_logical_lane = 9, + .start_lane = 8, + .end_lane = 9, .device_number = 1, .function_number = 2, .link_speed_capability = GEN_MAX, -- cgit v1.2.3