From bfc92cb94414b3a51490fefa203180914da06fbb Mon Sep 17 00:00:00 2001 From: Felix Held Date: Wed, 22 May 2024 00:42:13 +0200 Subject: device: drop unnecessary CHECK_REV_IN_OPROM_NAME option The CHECK_REV_IN_OPROM_NAME Kconfig option was introduced to solve the problem of the PCI VID/DID combination of the Picasso iGPU not being sufficient information to know which VGA BIOS file to run, so a new function that additionally checks the PCI revision of that device was introduced. Later it turned out that there might be a case where even that isn't sufficient, so the soc_is_raven2() function is used in the remap function to always use the correct VBIOS file. Picasso is the only SoC that selected the CHECK_REV_IN_OPROM_NAME Kconfig option, so all other SoCs are unaffected by this change. Now that we use the VBIOS images with only the PCI VID and DID in the CBFS file name for Picasso, SeaBIOS will find the VBIOS with the same ID as the iGPU in CBFS and we don't need the workaround to add a third VBIOS image via VGA_BIOS_DGPU_* that has the name that SeaBIOS expects. This will result in SeaBIOS now running the VBIOS that has the same PCI VID/DID as the hardware which will be the wrong one in the RV2 silicon showing the PCO silicon PCI VID/DID, but that was also the case with the VGA_BIOS_DGPU_* workaround where the board's Kconfig just selected one of the two possible images during build time and hoped that it was the correct one for that actual hardware. The only board where this patch might cause a regression compared to the old behavior is the AMD Cereme reference board with Pollock APU, but I'm not even sure if any coreboot developer still has one of those boards, so I'm willing to accept that. To properly solve the problem with SeaBIOS using the correct VBIOS file in all cases, we'd need to generate that info during coreboot runtime and somehow pass it to SeaBIOS, but that's out of scope for this patch. TEST=On Mandolin with PCO silicon, the display output in both SeaBIOS and Ubuntu still works. Booting Windows 10 via the pre-built EDK2 payload that I'm using also resulted in the display output working. Signed-off-by: Felix Held Change-Id: Ia6de533c536044698d85404427719b8f534870fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/82598 Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) --- src/mainboard/amd/mandolin/Kconfig | 13 ------------- 1 file changed, 13 deletions(-) (limited to 'src/mainboard/amd/mandolin') diff --git a/src/mainboard/amd/mandolin/Kconfig b/src/mainboard/amd/mandolin/Kconfig index 252404bb53..ce3af3ba74 100644 --- a/src/mainboard/amd/mandolin/Kconfig +++ b/src/mainboard/amd/mandolin/Kconfig @@ -106,19 +106,6 @@ config MANDOLIN_LPC Picasso's LPC bus signals are MUXed with some of the EMMC signals. Select this option if LPC signals are required. -#TODO: remove this hack to not break graphics in combination with SeaBIOS -config VGA_BIOS_DGPU_ID - string - default "1002,15d8" - help - The default VGA BIOS PCI vendor/device ID should be set to the - result of the map_oprom_vendev() function in northbridge.c. - -config VGA_BIOS_DGPU_FILE - string - default "3rdparty/amd_blobs/picasso/PicassoGenericVbios.bin" if BOARD_AMD_MANDOLIN - default "3rdparty/amd_blobs/picasso/Raven2GenericVbios.bin" if BOARD_AMD_CEREME - if !EM100 # EM100 defaults in soc/amd/common/blocks/spi/Kconfig config EFS_SPI_READ_MODE default 3 # Quad IO (1-1-4) -- cgit v1.2.3