From fec4db954e44a3fd23fedd2f51189c13c985eee9 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Wed, 2 Jun 2021 16:14:39 -0600 Subject: soc/amd/cezanne: Configure I2C Pad RX Select through devicetree Some of the I2C buses are required to operate at different voltage level compared to other I2C buses eg. I2C bus to Google Security Chip (GSC) should be at 1.8V level. By default, all the I2C buses are initialized to operate at 3.3 V. Add support to configure I2C pad RX select through devicetree and update the concerned devicetree. BUG=b:188538373 TEST=Build and boot to OS in Guybrush. Ensure that the communication with GSC is fine. Build Majolica mainboard. Change-Id: I595a64736fdac0274abffb68c5e521302275b845 Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/55149 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel Reviewed-by: Furquan Shaikh --- src/mainboard/amd/majolica/devicetree.cb | 6 ++++++ 1 file changed, 6 insertions(+) (limited to 'src/mainboard/amd/majolica') diff --git a/src/mainboard/amd/majolica/devicetree.cb b/src/mainboard/amd/majolica/devicetree.cb index dc73b844d0..5e9d971b9e 100644 --- a/src/mainboard/amd/majolica/devicetree.cb +++ b/src/mainboard/amd/majolica/devicetree.cb @@ -13,6 +13,12 @@ chip soc/amd/cezanne .flash_ch_en = 0, }" + # I2C Pad Control RX Select Configuration + register "i2c_pad_ctrl_rx_sel[0]" = "I2C_PAD_CTRL_RX_SEL_3_3V" + register "i2c_pad_ctrl_rx_sel[1]" = "I2C_PAD_CTRL_RX_SEL_3_3V" + register "i2c_pad_ctrl_rx_sel[2]" = "I2C_PAD_CTRL_RX_SEL_3_3V" + register "i2c_pad_ctrl_rx_sel[3]" = "I2C_PAD_CTRL_RX_SEL_3_3V" + register "s0ix_enable" = "true" register "pspp_policy" = "DXIO_PSPP_BALANCED" -- cgit v1.2.3