From 9bd9a90d6a0a47ede6286e2c5599ae7335e4b96a Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Sat, 20 Nov 2010 10:31:00 +0000 Subject: Unify DIMM SPD addressing. For Geode, change the addressing scheme to match the rest of the tree (0x50 instead of 0xa0). abuild tested. Signed-off-by: Patrick Georgi Acked-by: Uwe Hermann git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/amd/mahogany_fam10/romstage.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) (limited to 'src/mainboard/amd/mahogany_fam10') diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c index 3e6466e72c..abb2a114f8 100644 --- a/src/mainboard/amd/mahogany_fam10/romstage.c +++ b/src/mainboard/amd/mahogany_fam10/romstage.c @@ -57,6 +57,7 @@ static int smbus_read_byte(u32 device, u32 address); #include "southbridge/amd/rs780/rs780_early_setup.c" #include "southbridge/amd/sb700/sb700_early_setup.c" #include "northbridge/amd/amdfam10/debug.c" +#include static void activate_spd_rom(const struct mem_controller *ctrl) { @@ -90,11 +91,6 @@ static int spd_read_byte(u32 device, u32 address) #define RC00 0 #define RC01 1 -#define DIMM0 0x50 -#define DIMM1 0x51 -#define DIMM2 0x52 -#define DIMM3 0x53 - void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { -- cgit v1.2.3