From 01f7ab93359ae0fee5784d35effbcbe0b596df18 Mon Sep 17 00:00:00 2001
From: Kerry Sheh <shekairui@gmail.com>
Date: Thu, 19 Jan 2012 13:18:36 +0800
Subject: Inagua: Synchronize AMD/inagua mainboard.

AMD/persimmon mainboard code is derived from AMD/inagua mainbard.
Persimmom update a lot in the last few month, sync these modification to inagua.

Change-Id: Ia038e5a2b9550fe81bb075f31e30b98354758e9e
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/542
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
---
 src/mainboard/amd/inagua/romstage.c | 23 +++++++++++++----------
 1 file changed, 13 insertions(+), 10 deletions(-)

(limited to 'src/mainboard/amd/inagua/romstage.c')

diff --git a/src/mainboard/amd/inagua/romstage.c b/src/mainboard/amd/inagua/romstage.c
index 88c018ea3f..27022d4e67 100644
--- a/src/mainboard/amd/inagua/romstage.c
+++ b/src/mainboard/amd/inagua/romstage.c
@@ -17,6 +17,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <lib.h>
 #include <stdint.h>
 #include <string.h>
 #include <device/pci_def.h>
@@ -25,9 +26,11 @@
 #include <arch/stages.h>
 #include <device/pnp_def.h>
 #include <arch/romcc_io.h>
+#include <arch/cpu.h>
 #include <cpu/x86/lapic.h>
 #include <console/console.h>
 #include <console/loglevel.h>
+#include "agesawrapper.h"
 #include "cpu/x86/bist.h"
 #include "superio/smsc/kbc1100/kbc1100_early_init.c"
 #include "cpu/x86/lapic/boot_cpu.c"
@@ -35,21 +38,21 @@
 #include "pc80/i8259.c"
 #include "sb_cimx.h"
 #include "SBPLATFORM.h"
-#include <arch/cpu.h>
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx);
-u32 agesawrapper_amdinitmmio(void);
-u32 agesawrapper_amdinitreset(void);
-u32 agesawrapper_amdinitearly(void);
-u32 agesawrapper_amdinitenv(void);
-u32 agesawrapper_amdinitlate(void);
-u32 agesawrapper_amdinitpost(void);
-u32 agesawrapper_amdinitmid(void);
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 	u32 val;
 
+	/* all cores: allow caching of flash chip code and data
+	 * (there are no cache-as-ram reliability concerns with family 14h)
+	 */
+	__writemsr (0x20c, (0x0100000000ull - CONFIG_ROM_SIZE) | 5);
+	__writemsr (0x20d, (0x1000000000ull - CONFIG_ROM_SIZE) | 0x800);
+
+	/* all cores: set pstate 0 (1600 MHz) early to save a few ms of boot time
+	 */
+	__writemsr (0xc0010062, 0);
+
 	if (!cpu_init_detectedx && boot_cpu()) {
 		post_code(0x30);
 		sb_Poweron_Init();
-- 
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