From 31c5e07a04e90c03822d216d2dc92454b42e21ce Mon Sep 17 00:00:00 2001 From: Kimarie Hoot Date: Wed, 6 Mar 2013 16:18:09 -0700 Subject: AMD Inagua: Use SPD read code from F14 wrapper Changes: - Get rid of the inagua mainboard specific code and use the platform generic function wrapper that was added in change http://review.coreboot.org/#/c/2497/ AMD f14: Add SPD read functions to wrapper code - Move DIMM addresses into devicetree.cb - Add the ASF init that used to be in the SPD read code into mainboard_enable() Notes: - The DIMM reads only happen in romstage, so the function is not available in ramstage. Point the read-SPD callback to a generic function in ramstage. Change-Id: Id05227fcf18c6ab94ffe1beb50b533ab7b0535db Signed-off-by: Kimarie Hoot Reviewed-on: http://review.coreboot.org/2607 Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel --- src/mainboard/amd/inagua/devicetree.cb | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/mainboard/amd/inagua/devicetree.cb') diff --git a/src/mainboard/amd/inagua/devicetree.cb b/src/mainboard/amd/inagua/devicetree.cb index 3d8ccb4750..67c3a1af30 100644 --- a/src/mainboard/amd/inagua/devicetree.cb +++ b/src/mainboard/amd/inagua/devicetree.cb @@ -86,6 +86,11 @@ chip northbridge/amd/agesa/family14/root_complex device pci 18.5 on end device pci 18.6 on end device pci 18.7 on end + + register "spdAddrLookup" = " + { + { {0xA0, 0xA2}, {0x00, 0x00}, }, // socket 0 - Channel 0 & 1 - 8-bit SPD addresses + }" end #chip northbridge/amd/agesa/family14 # CPU side of HT root complex end #domain end #northbridge/amd/agesa/family14/root_complex -- cgit v1.2.3