From 6dfbb593077ea3edb9162431c2380a268d35fc4a Mon Sep 17 00:00:00 2001 From: Richard Spiegel Date: Thu, 15 Mar 2018 15:45:44 -0700 Subject: soc/amd/stoneyridge/southbridge.c: Remove configure_stoneyridge_uart The GPIO programming of configure_stoneyridge_UART() can be done by the early GPIO table, AOAC enabling was already removed. So configure_stoneyridge_uart() became redundant. Remove procedure configure_stoneyridge_uart(). BUG=b:74258015 TEST=Build and boot kahlee, observing serial output does not changes from previous serial output. Change-Id: Ie67051d7b90fa294090f6bfc518c6c074d98cc98 Signed-off-by: Richard Spiegel Reviewed-on: https://review.coreboot.org/25192 Reviewed-by: Garrett Kirkendall Reviewed-by: Martin Roth Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/mainboard/amd/gardenia/gpio.c | 10 ++++++++++ 1 file changed, 10 insertions(+) (limited to 'src/mainboard/amd/gardenia') diff --git a/src/mainboard/amd/gardenia/gpio.c b/src/mainboard/amd/gardenia/gpio.c index 2d73ee08d2..c274a76bc6 100644 --- a/src/mainboard/amd/gardenia/gpio.c +++ b/src/mainboard/amd/gardenia/gpio.c @@ -35,6 +35,16 @@ const struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = { {GPIO_116, Function1, FCH_GPIO_PULL_DOWN_ENABLE | INPUT }, /* SD power */ {GPIO_119, Function2, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, + /* GPIO_136 - UART0_FCH_RX_DEBUG_RX */ + {GPIO_136, Function0, INPUT }, + /* GPIO_137 - UART0_FCH_DEBUG_RTS */ + {GPIO_137, Function0, INPUT }, + /* GPIO_138 - UART0_FCH_TX_DEBUG_RX */ + {GPIO_138, Function0, INPUT }, + /* GPIO_142 - UART1_FCH_RTS */ + {GPIO_142, Function0, INPUT }, + /* GPIO_143 - UART1_FCH_TX */ + {GPIO_143, Function0, INPUT }, }; const struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = { -- cgit v1.2.3