From 2df118cdf04c72156ca92b940063288968ca7cea Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Fri, 5 May 2017 16:15:31 -0600 Subject: amd/gardenia: Switch to soc/amd/stoneyridge Switch Garnenia mainboard to single soc/ directory structure. Change-Id: I095804d603bcccf324d3244965081a9dccba62ae Signed-off-by: Marc Jones Reviewed-on: https://review.coreboot.org/19725 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/amd/gardenia/BiosCallOuts.c | 34 ++++++------ src/mainboard/amd/gardenia/BiosCallOuts.h | 46 ----------------- src/mainboard/amd/gardenia/Kconfig | 7 ++- src/mainboard/amd/gardenia/Makefile.inc | 2 +- src/mainboard/amd/gardenia/OemCustomize.c | 2 +- src/mainboard/amd/gardenia/acpi_tables.c | 2 +- src/mainboard/amd/gardenia/devicetree.cb | 86 ++++++++++++++----------------- src/mainboard/amd/gardenia/dsdt.asl | 16 +++--- src/mainboard/amd/gardenia/fchec.h | 2 +- src/mainboard/amd/gardenia/mainboard.c | 2 +- src/mainboard/amd/gardenia/mptable.c | 4 +- src/mainboard/amd/gardenia/romstage.c | 8 +-- 12 files changed, 75 insertions(+), 136 deletions(-) delete mode 100644 src/mainboard/amd/gardenia/BiosCallOuts.h (limited to 'src/mainboard/amd/gardenia') diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.c b/src/mainboard/amd/gardenia/BiosCallOuts.c index 23ce0c6304..f8d02a5614 100644 --- a/src/mainboard/amd/gardenia/BiosCallOuts.c +++ b/src/mainboard/amd/gardenia/BiosCallOuts.c @@ -15,22 +15,18 @@ #include #include -#include "AGESA.h" -#include "amdlib.h" -#include -#include -#include "Ids.h" -#include "heapManager.h" -#include "FchPlatform.h" -#include "cbfs.h" -#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) -#include "imc.h" -#endif -#include "hudson.h" +#include +#include +#include +#include +#include +#include +#include +#include +#include #include -#include "BiosCallOuts.h" -#include "northbridge/amd/pi/dimmSpd.h" -#include "northbridge/amd/pi/agesawrapper.h" +#include +#include static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); @@ -95,12 +91,12 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) } else if (StdHeader->Func == AMD_INIT_ENV) { FCH_DATA_BLOCK *FchParams_env = (FCH_DATA_BLOCK *)FchData; printk(BIOS_DEBUG, "Fch OEM config in INIT ENV "); -#if IS_ENABLED(CONFIG_HUDSON_IMC_FWM) +#if IS_ENABLED(CONFIG_STONEYRIDGE_IMC_FWM) oem_fan_control(FchParams_env); #endif /* XHCI configuration */ -#if CONFIG_HUDSON_XHCI_ENABLE +#if CONFIG_STONEYRIDGE_XHCI_ENABLE FchParams_env->Usb.Xhci0Enable = TRUE; #else FchParams_env->Usb.Xhci0Enable = FALSE; @@ -109,8 +105,8 @@ AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr) FchParams_env->Usb.USB30PortInit = 8; /* 8: If USB3 port is unremoveable. */ /* SATA configuration */ - FchParams_env->Sata.SataClass = CONFIG_HUDSON_SATA_MODE; - switch ((SATA_CLASS)CONFIG_HUDSON_SATA_MODE) { + FchParams_env->Sata.SataClass = CONFIG_STONEYRIDGE_SATA_MODE; + switch ((SATA_CLASS)CONFIG_STONEYRIDGE_SATA_MODE) { case SataRaid: case SataAhci: case SataAhci7804: diff --git a/src/mainboard/amd/gardenia/BiosCallOuts.h b/src/mainboard/amd/gardenia/BiosCallOuts.h deleted file mode 100644 index 8c2a047099..0000000000 --- a/src/mainboard/amd/gardenia/BiosCallOuts.h +++ /dev/null @@ -1,46 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2015 Advanced Micro Devices, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define FAN_INPUT_INTERNAL_DIODE 0 -#define FAN_INPUT_TEMP0 1 -#define FAN_INPUT_TEMP1 2 -#define FAN_INPUT_TEMP2 3 -#define FAN_INPUT_TEMP3 4 -#define FAN_INPUT_TEMP0_FILTER 5 -#define FAN_INPUT_ZERO 6 -#define FAN_INPUT_DISABLED 7 - -#define FAN_AUTOMODE (1 << 0) -#define FAN_LINEARMODE (1 << 1) -#define FAN_STEPMODE ~(1 << 1) -#define FAN_POLARITY_HIGH (1 << 2) -#define FAN_POLARITY_LOW ~(1 << 2) - -/* Normally, 4-wire fan runs at 25KHz and 3-wire fan runs at 100Hz */ -#define FREQ_28KHZ 0x0 -#define FREQ_25KHZ 0x1 -#define FREQ_23KHZ 0x2 -#define FREQ_21KHZ 0x3 -#define FREQ_29KHZ 0x4 -#define FREQ_18KHZ 0x5 -#define FREQ_100HZ 0xF7 -#define FREQ_87HZ 0xF8 -#define FREQ_58HZ 0xF9 -#define FREQ_44HZ 0xFA -#define FREQ_35HZ 0xFB -#define FREQ_29HZ 0xFC -#define FREQ_22HZ 0xFD -#define FREQ_14HZ 0xFE -#define FREQ_11HZ 0xFF diff --git a/src/mainboard/amd/gardenia/Kconfig b/src/mainboard/amd/gardenia/Kconfig index fdf8002fb2..58d952b1a4 100644 --- a/src/mainboard/amd/gardenia/Kconfig +++ b/src/mainboard/amd/gardenia/Kconfig @@ -17,15 +17,14 @@ if BOARD_AMD_GARDENIA config BOARD_SPECIFIC_OPTIONS # dummy def_bool y - select CPU_AMD_PI_00670F00_FP4 - select NORTHBRIDGE_AMD_PI_00670F00 - select SOUTHBRIDGE_AMD_PI_KERN + select SOC_AMD_STONEYRIDGE_FP4 select HAVE_OPTION_TABLE select HAVE_PIRQ_TABLE select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 select GFXUMA + select STONEYRIDGE_IMC_FWM config MAINBOARD_DIR string @@ -47,7 +46,7 @@ config ONBOARD_VGA_IS_PRIMARY bool default y -config HUDSON_LEGACY_FREE +config STONEYRIDGE_LEGACY_FREE bool default y diff --git a/src/mainboard/amd/gardenia/Makefile.inc b/src/mainboard/amd/gardenia/Makefile.inc index 72cd042ebf..ba5e3776fa 100644 --- a/src/mainboard/amd/gardenia/Makefile.inc +++ b/src/mainboard/amd/gardenia/Makefile.inc @@ -18,4 +18,4 @@ romstage-y += OemCustomize.c ramstage-y += BiosCallOuts.c ramstage-y += OemCustomize.c -ramstage-$(CONFIG_HUDSON_IMC_FWM) += fchec.c +ramstage-$(CONFIG_STONEYRIDGE_IMC_FWM) += fchec.c diff --git a/src/mainboard/amd/gardenia/OemCustomize.c b/src/mainboard/amd/gardenia/OemCustomize.c index 8f6c159bbb..5f9f50115d 100644 --- a/src/mainboard/amd/gardenia/OemCustomize.c +++ b/src/mainboard/amd/gardenia/OemCustomize.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include #define FILECODE PROC_GNB_PCIE_FAMILY_0X15_F15PCIECOMPLEXCONFIG_FILECODE diff --git a/src/mainboard/amd/gardenia/acpi_tables.c b/src/mainboard/amd/gardenia/acpi_tables.c index b09b7738e7..1b4f90caa2 100644 --- a/src/mainboard/amd/gardenia/acpi_tables.c +++ b/src/mainboard/amd/gardenia/acpi_tables.c @@ -13,7 +13,7 @@ * GNU General Public License for more details. */ -#include +#include #include #include diff --git a/src/mainboard/amd/gardenia/devicetree.cb b/src/mainboard/amd/gardenia/devicetree.cb index be070d067d..bb672b29e6 100644 --- a/src/mainboard/amd/gardenia/devicetree.cb +++ b/src/mainboard/amd/gardenia/devicetree.cb @@ -1,7 +1,7 @@ # # This file is part of the coreboot project. # -# Copyright (C) 2015-2016 Advanced Micro Devices, Inc. +# Copyright (C) 2015-2017 Advanced Micro Devices, Inc. # # This program is free software; you can redistribute it and/or modify # it under the terms of the GNU General Public License as published by @@ -12,55 +12,45 @@ # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the # GNU General Public License for more details. # -chip northbridge/amd/pi/00670F00/root_complex +chip soc/amd/stoneyridge + + register "spdAddrLookup" = " + { + { {0xA2, 0x00} }, // socket 0 - Channel 0, slots 0 & 1 + }" + device cpu_cluster 0 on - chip cpu/amd/pi/00670F00 - device lapic 10 on end - end + device lapic 10 on end end - device domain 0 on subsystemid 0x1022 0x1410 inherit - chip northbridge/amd/pi/00670F00 # CPU side of HT root complex - - chip northbridge/amd/pi/00670F00 # PCI side of HT root complex - device pci 0.0 on end # Root Complex - device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 - device pci 1.1 on end # Internal Multimedia - device pci 2.0 on end # PCIe Host Bridge - device pci 2.1 on end # x4 PCIe slot - device pci 2.2 on end # M.2 slot - device pci 2.3 on end # M.2 slot - device pci 2.4 on end # x1 PCIe slot - device pci 2.5 on end # Cardreader - end #chip northbridge/amd/pi/00670F00 - - chip southbridge/amd/pi/hudson # it is under NB/SB Link, but on the same pci bus - device pci 9.0 on end # PCIe Host Bridge - device pci 9.2 on end # HDA - device pci 10.0 on end # xHCI - device pci 11.0 on end # SATA - device pci 12.0 on end # EHCI - device pci 14.0 on # SM - chip drivers/generic/generic # dimm 0-0-0 - device i2c 51 on end - end - end # SM - device pci 14.3 on end # LPC 0x790e - device pci 14.7 on end # SD - end #chip southbridge/amd/pi/hudson - - device pci 18.0 on end - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - register "spdAddrLookup" = " - { - { {0xA2, 0x00} }, // socket 0 - Channel 0, slots 0 & 1 - }" - - end #chip northbridge/amd/pi/00670F00 # CPU side of HT root complex + device pci 0.0 on end # Root Complex + device pci 1.0 on end # Internal Graphics P2P bridge 0x98e4 + device pci 1.1 on end # Internal Multimedia + device pci 2.0 on end # PCIe Host Bridge + device pci 2.1 on end # x4 PCIe slot + device pci 2.2 on end # M.2 slot + device pci 2.3 on end # M.2 slot + device pci 2.4 on end # x1 PCIe slot + device pci 2.5 on end # Cardreader + # devices on the NB/SB Link, but on the same pci bus + device pci 9.0 on end # PCIe Host Bridge + device pci 9.2 on end # HDA + device pci 10.0 on end # xHCI + device pci 11.0 on end # SATA + device pci 12.0 on end # EHCI + device pci 14.0 on # SM + chip drivers/generic/generic # dimm 0-0-0 + device i2c 51 on end + end + end # SM + device pci 14.3 on end # LPC 0x790e + device pci 14.7 on end # SD + device pci 18.0 on end + device pci 18.1 on end + device pci 18.2 on end + device pci 18.3 on end + device pci 18.4 on end + device pci 18.5 on end end #domain -end #northbridge/amd/pi/00670F00/root_complex +end #chip soc/amd/stoneyridge diff --git a/src/mainboard/amd/gardenia/dsdt.asl b/src/mainboard/amd/gardenia/dsdt.asl index 0d36a60c68..2245ea2af0 100644 --- a/src/mainboard/amd/gardenia/dsdt.asl +++ b/src/mainboard/amd/gardenia/dsdt.asl @@ -32,20 +32,20 @@ DefinitionBlock ( #include "acpi/usb_oc.asl" /* PCI IRQ mapping for the Southbridge */ - #include + #include /* Describe the processor tree (\_PR) */ - #include + #include /* Contains the supported sleep states for this chipset */ - #include + #include /* Contains the Sleep methods (WAK, PTS, GTS, etc.) */ #include "acpi/sleep.asl" /* System Bus */ Scope(\_SB) { /* Start \_SB scope */ - /* global utility methods expected within the \_SB scope */ + /* global utility methods expected within the \_SB scope */ #include /* Describe IRQ Routing mapping for this platform (within the \_SB scope) */ @@ -60,14 +60,14 @@ DefinitionBlock ( Device(PCI0) { /* Describe the AMD Northbridge */ - #include + #include /* Describe the AMD Fusion Controller Hub Southbridge */ - #include + #include } /* Describe PCI INT[A-H] for the Southbridge */ - #include + #include /* Describe the devices in the Southbridge */ #include "acpi/carrizo_fch.asl" @@ -75,7 +75,7 @@ DefinitionBlock ( } /* End \_SB scope */ /* Describe SMBUS for the Southbridge */ - #include + #include /* Define the General Purpose Events for the platform */ #include "acpi/gpe.asl" diff --git a/src/mainboard/amd/gardenia/fchec.h b/src/mainboard/amd/gardenia/fchec.h index 7c22063f2b..9fb41b38c3 100644 --- a/src/mainboard/amd/gardenia/fchec.h +++ b/src/mainboard/amd/gardenia/fchec.h @@ -16,7 +16,7 @@ #ifndef AMD_GARDENIA_FCHEC #define AMD_GARDENIA_FCHEC -#include "imc.h" +#include #include "Porting.h" #include "AGESA.h" #include "FchCommonCfg.h" diff --git a/src/mainboard/amd/gardenia/mainboard.c b/src/mainboard/amd/gardenia/mainboard.c index acc9b7cfb9..947029620c 100644 --- a/src/mainboard/amd/gardenia/mainboard.c +++ b/src/mainboard/amd/gardenia/mainboard.c @@ -17,7 +17,7 @@ #include #include #include -#include +#include /*********************************************************** * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. diff --git a/src/mainboard/amd/gardenia/mptable.c b/src/mainboard/amd/gardenia/mptable.c index 1c74ae5359..0d9064f057 100644 --- a/src/mainboard/amd/gardenia/mptable.c +++ b/src/mainboard/amd/gardenia/mptable.c @@ -23,8 +23,8 @@ #include #include #include -#include "southbridge/amd/pi/hudson/hudson.h" -#include +#include +#include static void smp_add_mpc_entry(struct mp_config_table *mc, unsigned length) { diff --git a/src/mainboard/amd/gardenia/romstage.c b/src/mainboard/amd/gardenia/romstage.c index 75674a090a..678e1fbf83 100644 --- a/src/mainboard/amd/gardenia/romstage.c +++ b/src/mainboard/amd/gardenia/romstage.c @@ -22,7 +22,7 @@ #include #include #include -#include +#include void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) { @@ -35,9 +35,9 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) if (!cpu_init_detectedx && boot_cpu()) { post_code(0x30); -#if IS_ENABLED(CONFIG_HUDSON_UART) - configure_hudson_uart(); -#endif + if (IS_ENABLED(CONFIG_STONEYRIDGE_UART)) + configure_hudson_uart(); + post_code(0x31); console_init(); } -- cgit v1.2.3