From 3fe3f0409cd340112d62283bf79be9f106a6dff8 Mon Sep 17 00:00:00 2001 From: Justin TerAvest Date: Wed, 14 Feb 2018 19:10:15 -0700 Subject: soc/amd/stoneyridge: Normalize GPIO init This makes the flow for GPIO initialization more closely follow that what is performed for other boards so that it's easier to read the flow (and stops relying on BS_WRITE_TABLES). BUG=b:72875858 TEST=Built and booted grunt, built gardenia. Change-Id: Ic97db96581a69798b193a6bdeb93644f6a74fc9d Signed-off-by: Justin TerAvest Reviewed-on: https://review.coreboot.org/23679 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/mainboard/amd/gardenia/gpio.c | 61 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) create mode 100644 src/mainboard/amd/gardenia/gpio.c (limited to 'src/mainboard/amd/gardenia/gpio.c') diff --git a/src/mainboard/amd/gardenia/gpio.c b/src/mainboard/amd/gardenia/gpio.c new file mode 100644 index 0000000000..2d73ee08d2 --- /dev/null +++ b/src/mainboard/amd/gardenia/gpio.c @@ -0,0 +1,61 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Advanced Micro Devices, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include +#include +#include +#include +#include + +#include "gpio.h" + +/* + * As a rule of thumb, GPIO pins used by coreboot should be initialized at + * bootblock while GPIO pins used only by the OS should be initialized at + * ramstage. + */ +const struct soc_amd_stoneyridge_gpio gpio_set_stage_reset[] = { + /* NFC PU */ + {GPIO_64, Function0, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, + /* PCIe presence detect */ + {GPIO_69, Function0, FCH_GPIO_PULL_UP_ENABLE | INPUT }, + /* MUX for Power Express Eval */ + {GPIO_116, Function1, FCH_GPIO_PULL_DOWN_ENABLE | INPUT }, + /* SD power */ + {GPIO_119, Function2, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, +}; + +const struct soc_amd_stoneyridge_gpio gpio_set_stage_ram[] = { + /* BT radio disable */ + {GPIO_14, Function1, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, + /* NFC wake */ + {GPIO_65, Function0, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, + /* Webcam */ + {GPIO_66, Function0, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, + /* GPS sleep */ + {GPIO_70, Function0, FCH_GPIO_PULL_UP_ENABLE | OUTPUT_H }, +}; + +const struct soc_amd_stoneyridge_gpio *early_gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_reset); + return gpio_set_stage_reset; +} + +const struct soc_amd_stoneyridge_gpio *gpio_table(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage_ram); + return gpio_set_stage_ram; +} -- cgit v1.2.3