From 8ab989e31561cea0c6af5d5e242dd2be97bc73b4 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 30 Jul 2016 17:46:17 +0200 Subject: src/mainboard: Capitalize ROM, RAM, CPU and APIC Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/15987 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth --- src/mainboard/amd/dinar/buildOpts.c | 4 ++-- src/mainboard/amd/dinar/romstage.c | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) (limited to 'src/mainboard/amd/dinar') diff --git a/src/mainboard/amd/dinar/buildOpts.c b/src/mainboard/amd/dinar/buildOpts.c index 3fd9c48885..e237ff0b79 100644 --- a/src/mainboard/amd/dinar/buildOpts.c +++ b/src/mainboard/amd/dinar/buildOpts.c @@ -54,10 +54,10 @@ #define POWER_DOWN_BY_CHANNEL 0 ///< Channel power down mode #define POWER_DOWN_BY_CHIP_SELECT 1 ///< Chip select power down mode -/* Select the cpu family. */ +/* Select the CPU family. */ -/* Select the cpu socket type. */ +/* Select the CPU socket type. */ #define INSTALL_G34_SOCKET_SUPPORT TRUE #define INSTALL_C32_SOCKET_SUPPORT FALSE #define INSTALL_S1G3_SOCKET_SUPPORT FALSE diff --git a/src/mainboard/amd/dinar/romstage.c b/src/mainboard/amd/dinar/romstage.c index 70cd5e3586..bc5d3126f2 100644 --- a/src/mainboard/amd/dinar/romstage.c +++ b/src/mainboard/amd/dinar/romstage.c @@ -94,7 +94,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) post_code(0x43); - printk(BIOS_DEBUG, "Disabling cache as ram "); + printk(BIOS_DEBUG, "Disabling cache as RAM "); disable_cache_as_ram(); printk(BIOS_DEBUG, "done\n"); -- cgit v1.2.3