From 9bd9a90d6a0a47ede6286e2c5599ae7335e4b96a Mon Sep 17 00:00:00 2001 From: Patrick Georgi Date: Sat, 20 Nov 2010 10:31:00 +0000 Subject: Unify DIMM SPD addressing. For Geode, change the addressing scheme to match the rest of the tree (0x50 instead of 0xa0). abuild tested. Signed-off-by: Patrick Georgi Acked-by: Uwe Hermann git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6099 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/amd/db800/romstage.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) (limited to 'src/mainboard/amd/db800') diff --git a/src/mainboard/amd/db800/romstage.c b/src/mainboard/amd/db800/romstage.c index 0f2ec7fce0..8977b27bd4 100644 --- a/src/mainboard/amd/db800/romstage.c +++ b/src/mainboard/amd/db800/romstage.c @@ -30,6 +30,7 @@ #include #include #include "southbridge/amd/cs5536/cs5536.h" +#include #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) @@ -45,8 +46,6 @@ static inline int spd_read_byte(unsigned int device, unsigned int address) #define ManualConf 0 /* Do automatic strapped PLL config */ #define PLLMSRhi 0x000005DD /* Manual settings for the PLL */ #define PLLMSRlo 0x00DE60EE -#define DIMM0 0xA0 -#define DIMM1 0xA2 #include "northbridge/amd/lx/raminit.h" #include "northbridge/amd/lx/pll_reset.c" -- cgit v1.2.3