From 1acb133e2d76a285f42198f0daba0f3ab16dc82c Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 13 Jun 2022 17:19:04 +0200 Subject: mb/amd/chausie/devicetree: add PCIe clock output configuration The general purpose PCIe clock outputs 0, 1 and 3 are used with their corresponding clock request pins, so set the gpp_clk_config to GPP_CLK_REQ for those and disable the unused output 2. This matches the DXIO descriptor in port_descriptors.c. Signed-off-by: Felix Held Change-Id: I38ab8d6d824617509fdd18f06d5593889ec50666 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65112 Reviewed-by: Fred Reitberger Reviewed-by: Raul Rangel Tested-by: build bot (Jenkins) --- src/mainboard/amd/chausie/devicetree.cb | 5 +++++ 1 file changed, 5 insertions(+) (limited to 'src/mainboard/amd/chausie') diff --git a/src/mainboard/amd/chausie/devicetree.cb b/src/mainboard/amd/chausie/devicetree.cb index b7e0aa1a48..c0806a5c07 100644 --- a/src/mainboard/amd/chausie/devicetree.cb +++ b/src/mainboard/amd/chausie/devicetree.cb @@ -149,6 +149,11 @@ chip soc/amd/sabrina .PhyP3CpmP4Support = 0, }" + register "gpp_clk_config[0]" = "GPP_CLK_REQ" + register "gpp_clk_config[1]" = "GPP_CLK_REQ" + register "gpp_clk_config[2]" = "GPP_CLK_OFF" + register "gpp_clk_config[3]" = "GPP_CLK_REQ" + device domain 0 on device ref iommu on end device ref gpp_bridge_0 on end # GBE -- cgit v1.2.3