From c4eb45fa85d9860ce94829c6c977b9e28a297bf9 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 13 Feb 2021 02:36:02 +0100 Subject: soc/amd/picasso: introduce and use chipset device tree The chipset devicetree only has the essential PCIe devices enabled that are needed for the SoC code to work. It also defines aliases for all PCIe devices that can be used to reference the devices in the mainboard- specific devicetrees and devicetree overrides. To make the change easier to review that part will be done in a follow-up patch. Despite missing in the PPR, device pci 18.7 exists on Picasso. Signed-off-by: Felix Held Change-Id: I6b7c3fd32579a23539594672593a243172c161c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/50626 Tested-by: build bot (Jenkins) Reviewed-by: Raul Rangel --- src/mainboard/amd/bilby/devicetree.cb | 16 ---------------- 1 file changed, 16 deletions(-) (limited to 'src/mainboard/amd/bilby') diff --git a/src/mainboard/amd/bilby/devicetree.cb b/src/mainboard/amd/bilby/devicetree.cb index 8adbaa2f50..7015185805 100644 --- a/src/mainboard/amd/bilby/devicetree.cb +++ b/src/mainboard/amd/bilby/devicetree.cb @@ -138,18 +138,12 @@ chip soc/amd/picasso register "pspp_policy" = "DXIO_PSPP_BALANCED" - device cpu_cluster 0 on - device lapic 0 on end - end device domain 0 on subsystemid 0x1022 0x1510 inherit - device pci 0.0 on end # Root Complex device pci 0.2 on end # IOMMU - device pci 1.0 on end # Dummy Host Bridge device pci 1.1 on end # GPP Bridge 0 device pci 1.2 on end # GPP Bridge 1 device pci 1.5 on end # NVMe - device pci 8.0 on end # Dummy Host Bridge device pci 8.1 on # Bridge to Bus A device pci 0.0 on end # Internal GPU device pci 0.1 on end # Display HDA @@ -165,20 +159,10 @@ chip soc/amd/picasso device pci 0.1 off end # integrated Ethernet MAC device pci 0.2 off end # integrated Ethernet MAC end - device pci 14.0 on end # SMBus device pci 14.3 on # D14F3 bridge chip superio/smsc/sio1036 # optional debug card end end - device pci 14.6 off end # SDHCI - device pci 18.0 on end # Data fabric [0-7] - device pci 18.1 on end - device pci 18.2 on end - device pci 18.3 on end - device pci 18.4 on end - device pci 18.5 on end - device pci 18.6 on end - device pci 18.7 on end end # domain device mmio 0xfedc9000 on end # UART0 -- cgit v1.2.3