From 0fec867e32a2df821e5a3569496b1dda7a2b1d5f Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 25 May 2021 21:07:23 +0200 Subject: soc/amd/picasso: add devicetree setting for PSPP policy Since the default for the corresponding UPD of the Picasso FSP is DXIO_PSPP_POWERSAVE and the devicetree default is DXIO_PSPP_PERFORMANCE, add a deviectree setting for each board that's using the Picasso SoC code to not change the setting for the existing boards. Signed-off-by: Felix Held Change-Id: I0008ebb0c0f339ed3bdf24ab95a20aa83d5be2c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/54934 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/mainboard/amd/bilby/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/amd/bilby') diff --git a/src/mainboard/amd/bilby/devicetree.cb b/src/mainboard/amd/bilby/devicetree.cb index a3385b92be..7797c3e44d 100644 --- a/src/mainboard/amd/bilby/devicetree.cb +++ b/src/mainboard/amd/bilby/devicetree.cb @@ -136,6 +136,8 @@ chip soc/amd/picasso register "gpp_clk_config[5]" = "GPP_CLK_REQ" register "gpp_clk_config[6]" = "GPP_CLK_REQ" + register "pspp_policy" = "DXIO_PSPP_POWERSAVE" + device cpu_cluster 0 on device lapic 0 on end end -- cgit v1.2.3