From 187543c90da824198a7da2b531665f4d2dece243 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Sun, 20 Nov 2016 11:03:13 +0200 Subject: AMD binaryPI: Switch to MMCONF_SUPPORT_DEFAULT MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Vendorcode always does PCI MMCONF access once it is enabled via MSR. In coreboot proper, we don't give opportunity to make pci_read/write calls before PCI MMCONF is enabled via MSR. This happens early in romstage amd_initmmio() for all cores. Change-Id: Id6ec25706b52441259e7dc1582f9a4ce8b154083 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/17534 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/mainboard/amd/bettong/romstage.c | 1 + 1 file changed, 1 insertion(+) (limited to 'src/mainboard/amd/bettong/romstage.c') diff --git a/src/mainboard/amd/bettong/romstage.c b/src/mainboard/amd/bettong/romstage.c index c3e2aa4b62..6b12afc83b 100644 --- a/src/mainboard/amd/bettong/romstage.c +++ b/src/mainboard/amd/bettong/romstage.c @@ -32,6 +32,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx) void *resume_backup_memory; #endif + /* Must come first to enable PCI MMCONF. */ amd_initmmio(); hudson_lpc_port80(); -- cgit v1.2.3