From 6ca7636c8f52560e732cdd5b1c7829cda5aa2bde Mon Sep 17 00:00:00 2001 From: "arch import user (historical)" Date: Wed, 6 Jul 2005 17:17:25 +0000 Subject: Revision: linuxbios@linuxbios.org--devel/freebios--devel--2.0--patch-51 Creator: Yinghai Lu cache_as_ram for AMD and some intel git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1967 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/mainboard/Iwill/DK8S2/Options.lb | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/mainboard/Iwill/DK8S2/Options.lb') diff --git a/src/mainboard/Iwill/DK8S2/Options.lb b/src/mainboard/Iwill/DK8S2/Options.lb index 373d1a98a9..d7b694d1f8 100644 --- a/src/mainboard/Iwill/DK8S2/Options.lb +++ b/src/mainboard/Iwill/DK8S2/Options.lb @@ -51,6 +51,8 @@ uses CC uses HOSTCC uses OBJCOPY +uses CONFIG_USE_INIT + ## ROM_SIZE is the size of boot ROM that this board will use. default ROM_SIZE=524288 -- cgit v1.2.3