From a634dab1a66d47023a16eaa1ec0a6f0eec688ef0 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 25 Jul 2020 11:27:49 +0200 Subject: skylake boards: Factor out copy-pasted PIRQ routes MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Put them in common code just in case something depends on the values. Change-Id: Ief526efcbd5ba5546572da1bc6bb6d86729f4e54 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/43851 Reviewed-by: Nico Huber Reviewed-by: Arthur Heymans Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- src/mainboard/51nb/x210/devicetree.cb | 9 --------- 1 file changed, 9 deletions(-) (limited to 'src/mainboard/51nb') diff --git a/src/mainboard/51nb/x210/devicetree.cb b/src/mainboard/51nb/x210/devicetree.cb index b610904a9e..8e775b51a3 100644 --- a/src/mainboard/51nb/x210/devicetree.cb +++ b/src/mainboard/51nb/x210/devicetree.cb @@ -71,15 +71,6 @@ chip soc/intel/skylake register "serirq_mode" = "SERIRQ_CONTINUOUS" - register "pirqa_routing" = "PCH_IRQ11" - register "pirqb_routing" = "PCH_IRQ10" - register "pirqc_routing" = "PCH_IRQ11" - register "pirqd_routing" = "PCH_IRQ11" - register "pirqe_routing" = "PCH_IRQ11" - register "pirqf_routing" = "PCH_IRQ11" - register "pirqg_routing" = "PCH_IRQ11" - register "pirqh_routing" = "PCH_IRQ11" - register "PmConfigPciClockRun" = "1" # Enable Root Ports 3, 4 and 9 -- cgit v1.2.3