From b09e5001f3071e82ccf7ec64c9cf9a4768d660b1 Mon Sep 17 00:00:00 2001 From: Philipp Hug Date: Wed, 6 Feb 2019 06:48:51 +0100 Subject: riscv: Add initial support for 32bit boards * Adding separate targets for 32bit and 64bit qemu * Using the riscv64 toolchain for 32bit builds requires setting -m elf32lriscv * rv32/rv64 is currently configured with ARCH_RISCV_RV32/RV64 and not per stage. This should probably be changed later. TEST=Boots to "Payload not loaded." on 32bit qemu using the following commands: util/riscv/make-spike-elf.sh build/coreboot.rom build/coreboot.elf qemu-system-riscv32 -M virt -m 1024M -nographic -kernel build/coreboot.elf Change-Id: I35e59b459d1770df10b51fe9e77dcc474d7c75a0 Signed-off-by: Philipp Hug Reviewed-on: https://review.coreboot.org/c/31253 Tested-by: build bot (Jenkins) Reviewed-by: ron minnich --- src/lib/libgcc.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) (limited to 'src/lib') diff --git a/src/lib/libgcc.c b/src/lib/libgcc.c index 99a0749a45..88b3f9be01 100644 --- a/src/lib/libgcc.c +++ b/src/lib/libgcc.c @@ -20,7 +20,8 @@ * in case GCC does not have an assembly version for this arch. */ -#if !IS_ENABLED(CONFIG_ARCH_X86) /* work around lack of --gc-sections on x86 */ +#if !IS_ENABLED(CONFIG_ARCH_X86) /* work around lack of --gc-sections on x86 */ \ + && !IS_ENABLED(CONFIG_ARCH_RISCV_RV32) /* defined in rv32 libgcc.a */ int __clzsi2(u32 a); int __clzsi2(u32 a) { -- cgit v1.2.3