From 6739a6a89f5b7526bddc63b16ffc519c39d788dd Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 4 Jul 2023 10:09:59 +0300 Subject: vboot: Fix S3 resume with stage_cache MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit In VBOOT_STARTS_IN_ROMSTAGE=y case, vboot_run_logic() did not get called when postcar was loaded from TSEG stage cache on ACPI S3 resume path. Resume failed as MP init attempts to access microcode update from unverified FW_MAIN_A/B section. In a similar fashion, for POSTCAR=n, loading ramstage from TSEG stage cache would bypass the call to vboot_run_logic(). TEST=samsung/lumpy with VBOOT_STARTS_IN_ROMSTAGE=y is able to complete S3 resume. Change-Id: I77fe86d5fd89d22b5ef6f43e65a85a4ccd3259d9 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/76209 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Julius Werner --- src/lib/prog_loaders.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) (limited to 'src/lib') diff --git a/src/lib/prog_loaders.c b/src/lib/prog_loaders.c index 17d946eac9..9e661c5956 100644 --- a/src/lib/prog_loaders.c +++ b/src/lib/prog_loaders.c @@ -92,6 +92,8 @@ void __noreturn run_ramstage(void) else timestamp_add_now(TS_ROMSTAGE_END); + vboot_run_logic(); + /* * Only x86 systems using ramstage stage cache currently take the same * firmware path on resume. @@ -99,8 +101,6 @@ void __noreturn run_ramstage(void) if (ENV_X86 && resume_from_stage_cache()) run_ramstage_from_resume(&ramstage); - vboot_run_logic(); - timestamp_add_now(TS_COPYRAM_START); if (ENV_X86) { -- cgit v1.2.3