From 551cff08d540ced6817cfe230750a311d573c209 Mon Sep 17 00:00:00 2001 From: Vladimir Serbinenko Date: Sat, 10 Oct 2015 23:58:08 +0200 Subject: Derive lvds_dual_channel from EDID timings. Based on the info by Felix Held. Change-Id: Iab84dd8a0e3c942da20a6e21db5510e4ad16cadd Signed-off-by: Vladimir Serbinenko Reviewed-on: http://review.coreboot.org/11857 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/lib/edid.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) (limited to 'src/lib') diff --git a/src/lib/edid.c b/src/lib/edid.c index 68cc38a278..d0056788a3 100644 --- a/src/lib/edid.c +++ b/src/lib/edid.c @@ -446,6 +446,21 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension, if (! c->did_detailed_timing){ /* Edid contains pixel clock in terms of 10KHz */ out->mode.pixel_clock = (x[0] + (x[1] << 8)) * 10; + /* + LVDS supports following pixel clocks + 25000...112000 kHz: single channel + 80000...224000 kHz: dual channel + There is some overlap in theoretically supported + pixel clock between single-channel and dual-channel. + In practice with current panels all panels + <= 75200 kHz: single channel + >= 97750 kHz: dual channel + We have no samples between those values, so put a + threshold at 95000 kHz. If we get anything over + 95000 kHz with single channel, we can make this + more sofisticated but it's currently not needed. + */ + out->mode.lvds_dual_channel = (out->mode.pixel_clock >= 95000); extra_info.x_mm = (x[12] + ((x[14] & 0xF0) << 4)); extra_info.y_mm = (x[13] + ((x[14] & 0x0F) << 8)); out->mode.ha = (x[2] + ((x[4] & 0xF0) << 4)); -- cgit v1.2.3