From 9fe4d797a37671a65053add3f7cca27397db0b9b Mon Sep 17 00:00:00 2001 From: Stefan Reinauer Date: Sat, 16 Jan 2010 17:53:38 +0000 Subject: coreboot used to have two different "APIs" for memory accesses: read32(unsigned long addr) vs readl(void *addr) and write32(unsigned long addr, uint32_t value) vs writel(uint32_t value, void *addr) read32 was only available in __PRE_RAM__ stage, while readl was used in stage2. Some unclean implementations then made readl available to __PRE_RAM__ too which results in really messy includes and code. This patch fixes all code to use the read32/write32 variant, so that we can remove readl/writel in another patch. Signed-off-by: Stefan Reinauer Acked-by: Ronald G. Minnich git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5022 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/lib/usbdebug_direct.c | 92 +++++++++++++++++++++++------------------------ 1 file changed, 46 insertions(+), 46 deletions(-) (limited to 'src/lib/usbdebug_direct.c') diff --git a/src/lib/usbdebug_direct.c b/src/lib/usbdebug_direct.c index 1fd1113867..c9fe68ecfe 100644 --- a/src/lib/usbdebug_direct.c +++ b/src/lib/usbdebug_direct.c @@ -83,7 +83,7 @@ static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug) unsigned ctrl; int loop = 0x100000; do { - ctrl = readl(&ehci_debug->control); + ctrl = read32(&ehci_debug->control); /* Stop when the transaction is finished */ if (ctrl & DBGP_DONE) break; @@ -94,7 +94,7 @@ static int dbgp_wait_until_complete(struct ehci_dbg_port *ehci_debug) /* Now that we have observed the completed transaction, * clear the done bit. */ - writel(ctrl | DBGP_DONE, &ehci_debug->control); + write32(&ehci_debug->control, ctrl | DBGP_DONE); return (ctrl & DBGP_ERROR) ? -DBGP_ERRCODE(ctrl) : DBGP_LEN(ctrl); } @@ -119,9 +119,9 @@ static int dbgp_wait_until_done(struct ehci_dbg_port *ehci_debug, unsigned ctrl) int loop = 3; retry: - writel(ctrl | DBGP_GO, &ehci_debug->control); + write32(&ehci_debug->control, ctrl | DBGP_GO); ret = dbgp_wait_until_complete(ehci_debug); - pids = readl(&ehci_debug->pids); + pids = read32(&ehci_debug->pids); lpid = DBGP_PID_GET(pids); if (ret < 0) @@ -151,8 +151,8 @@ static void dbgp_set_data(struct ehci_dbg_port *ehci_debug, const void *buf, int lo |= bytes[i] << (8*i); for (; i < 8 && i < size; i++) hi |= bytes[i] << (8*(i - 4)); - writel(lo, &ehci_debug->data03); - writel(hi, &ehci_debug->data47); + write32(&ehci_debug->data03, lo); + write32(&ehci_debug->data47, hi); } static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size) @@ -160,8 +160,8 @@ static void dbgp_get_data(struct ehci_dbg_port *ehci_debug, void *buf, int size) unsigned char *bytes = buf; unsigned lo, hi; int i; - lo = readl(&ehci_debug->data03); - hi = readl(&ehci_debug->data47); + lo = read32(&ehci_debug->data03); + hi = read32(&ehci_debug->data47); for (i = 0; i < 4 && i < size; i++) bytes[i] = (lo >> (8*i)) & 0xff; for (; i < 8 && i < size; i++) @@ -177,17 +177,17 @@ static int dbgp_bulk_write(struct ehci_dbg_port *ehci_debug, unsigned devnum, un addr = DBGP_EPADDR(devnum, endpoint); - pids = readl(&ehci_debug->pids); + pids = read32(&ehci_debug->pids); pids = DBGP_PID_UPDATE(pids, USB_PID_OUT); - ctrl = readl(&ehci_debug->control); + ctrl = read32(&ehci_debug->control); ctrl = DBGP_LEN_UPDATE(ctrl, size); ctrl |= DBGP_OUT; ctrl |= DBGP_GO; dbgp_set_data(ehci_debug, bytes, size); - writel(addr, &ehci_debug->address); - writel(pids, &ehci_debug->pids); + write32(&ehci_debug->address, addr); + write32(&ehci_debug->pids, pids); ret = dbgp_wait_until_done(ehci_debug, ctrl); if (ret < 0) { @@ -211,16 +211,16 @@ static int dbgp_bulk_read(struct ehci_dbg_port *ehci_debug, unsigned devnum, uns addr = DBGP_EPADDR(devnum, endpoint); - pids = readl(&ehci_debug->pids); + pids = read32(&ehci_debug->pids); pids = DBGP_PID_UPDATE(pids, USB_PID_IN); - ctrl = readl(&ehci_debug->control); + ctrl = read32(&ehci_debug->control); ctrl = DBGP_LEN_UPDATE(ctrl, size); ctrl &= ~DBGP_OUT; ctrl |= DBGP_GO; - writel(addr, &ehci_debug->address); - writel(pids, &ehci_debug->pids); + write32(&ehci_debug->address, addr); + write32(&ehci_debug->pids, pids); ret = dbgp_wait_until_done(ehci_debug, ctrl); if (ret < 0) return ret; @@ -256,15 +256,15 @@ static int dbgp_control_msg(struct ehci_dbg_port *ehci_debug, unsigned devnum, i pids = DBGP_PID_SET(USB_PID_DATA0, USB_PID_SETUP); addr = DBGP_EPADDR(devnum, 0); - ctrl = readl(&ehci_debug->control); + ctrl = read32(&ehci_debug->control); ctrl = DBGP_LEN_UPDATE(ctrl, sizeof(req)); ctrl |= DBGP_OUT; ctrl |= DBGP_GO; /* Send the setup message */ dbgp_set_data(ehci_debug, &req, sizeof(req)); - writel(addr, &ehci_debug->address); - writel(pids, &ehci_debug->pids); + write32(&ehci_debug->address, addr); + write32(&ehci_debug->pids, pids); ret = dbgp_wait_until_done(ehci_debug, ctrl); if (ret < 0) return ret; @@ -282,25 +282,25 @@ static int ehci_reset_port(struct ehci_regs *ehci_regs, int port) int loop; /* Reset the usb debug port */ - portsc = readl(&ehci_regs->port_status[port - 1]); + portsc = read32(&ehci_regs->port_status[port - 1]); portsc &= ~PORT_PE; portsc |= PORT_RESET; - writel(portsc, &ehci_regs->port_status[port - 1]); + write32(&ehci_regs->port_status[port - 1], portsc); delay = HUB_ROOT_RESET_TIME; for (delay_time = 0; delay_time < HUB_RESET_TIMEOUT; delay_time += delay) { dbgp_mdelay(delay); - portsc = readl(&ehci_regs->port_status[port - 1]); + portsc = read32(&ehci_regs->port_status[port - 1]); if (portsc & PORT_RESET) { /* force reset to complete */ loop = 2; - writel(portsc & ~(PORT_RWC_BITS | PORT_RESET), - &ehci_regs->port_status[port - 1]); + write32(&ehci_regs->port_status[port - 1], + portsc & ~(PORT_RWC_BITS | PORT_RESET)); do { dbgp_mdelay(delay); - portsc = readl(&ehci_regs->port_status[port - 1]); + portsc = read32(&ehci_regs->port_status[port - 1]); delay_time += delay; } while ((portsc & PORT_RESET) && (--loop > 0)); if (!loop) { @@ -329,7 +329,7 @@ static int ehci_wait_for_port(struct ehci_regs *ehci_regs, int port) int ret, reps; for (reps = 0; reps < 3; reps++) { dbgp_mdelay(100); - status = readl(&ehci_regs->status); + status = read32(&ehci_regs->status); if (status & STS_PCD) { ret = ehci_reset_port(ehci_regs, port); if (ret == 0) @@ -366,7 +366,7 @@ static void usbdebug_direct_init(unsigned ehci_bar, unsigned offset, struct ehci unsigned playtimes = 3; ehci_caps = (struct ehci_caps *)ehci_bar; - ehci_regs = (struct ehci_regs *)(ehci_bar + HC_LENGTH(readl(&ehci_caps->hc_capbase))); + ehci_regs = (struct ehci_regs *)(ehci_bar + HC_LENGTH(read32(&ehci_caps->hc_capbase))); ehci_debug = (struct ehci_dbg_port *)(ehci_bar + offset); info->ehci_debug = (void *)0; @@ -375,7 +375,7 @@ try_next_time: port_map_tried = 0; try_next_port: - hcs_params = readl(&ehci_caps->hcs_params); + hcs_params = read32(&ehci_caps->hcs_params); debug_port = HCS_DEBUG_PORT(hcs_params); n_ports = HCS_N_PORTS(hcs_params); @@ -385,7 +385,7 @@ try_next_port: #if 1 for (i = 1; i <= n_ports; i++) { - portsc = readl(&ehci_regs->port_status[i-1]); + portsc = read32(&ehci_regs->port_status[i-1]); dbgp_printk("PORTSC #%d: %08x\n", i, portsc); } #endif @@ -400,11 +400,11 @@ try_next_port: /* Reset the EHCI controller */ loop = 10; - cmd = readl(&ehci_regs->command); + cmd = read32(&ehci_regs->command); cmd |= CMD_RESET; - writel(cmd, &ehci_regs->command); + write32(&ehci_regs->command, cmd); do { - cmd = readl(&ehci_regs->command); + cmd = read32(&ehci_regs->command); } while ((cmd & CMD_RESET) && (--loop > 0)); if(!loop) @@ -413,24 +413,24 @@ try_next_port: dbgp_printk("EHCI controller reset successfully.\n"); /* Claim ownership, but do not enable yet */ - ctrl = readl(&ehci_debug->control); + ctrl = read32(&ehci_debug->control); ctrl |= DBGP_OWNER; ctrl &= ~(DBGP_ENABLED | DBGP_INUSE); - writel(ctrl, &ehci_debug->control); + write32(&ehci_debug->control, ctrl); /* Start the ehci running */ - cmd = readl(&ehci_regs->command); + cmd = read32(&ehci_regs->command); cmd &= ~(CMD_LRESET | CMD_IAAD | CMD_PSE | CMD_ASE | CMD_RESET); cmd |= CMD_RUN; - writel(cmd, &ehci_regs->command); + write32(&ehci_regs->command, cmd); /* Ensure everything is routed to the EHCI */ - writel(FLAG_CF, &ehci_regs->configured_flag); + write32(&ehci_regs->configured_flag, FLAG_CF); /* Wait until the controller is no longer halted */ loop = 10; do { - status = readl(&ehci_regs->status); + status = read32(&ehci_regs->status); } while ((status & STS_HALT) && (--loop>0)); if(!loop) { @@ -448,21 +448,21 @@ try_next_port: dbgp_printk("EHCI done waiting for port.\n"); /* Enable the debug port */ - ctrl = readl(&ehci_debug->control); + ctrl = read32(&ehci_debug->control); ctrl |= DBGP_CLAIM; - writel(ctrl, &ehci_debug->control); - ctrl = readl(&ehci_debug->control); + write32(&ehci_debug->control, ctrl); + ctrl = read32(&ehci_debug->control); if ((ctrl & DBGP_CLAIM) != DBGP_CLAIM) { dbgp_printk("No device in EHCI debug port.\n"); - writel(ctrl & ~DBGP_CLAIM, &ehci_debug->control); + write32(&ehci_debug->control, ctrl & ~DBGP_CLAIM); goto err; } dbgp_printk("EHCI debug port enabled.\n"); /* Completely transfer the debug device to the debug controller */ - portsc = readl(&ehci_regs->port_status[debug_port - 1]); + portsc = read32(&ehci_regs->port_status[debug_port - 1]); portsc &= ~PORT_PE; - writel(portsc, &ehci_regs->port_status[debug_port - 1]); + write32(&ehci_regs->port_status[debug_port - 1], portsc); dbgp_mdelay(100); @@ -529,9 +529,9 @@ try_next_port: return; err: /* Things didn't work so remove my claim */ - ctrl = readl(&ehci_debug->control); + ctrl = read32(&ehci_debug->control); ctrl &= ~(DBGP_CLAIM | DBGP_OUT); - writel(ctrl, &ehci_debug->control); + write32(&ehci_debug->control, ctrl); next_debug_port: port_map_tried |= (1<<(debug_port-1)); -- cgit v1.2.3