From 7274800ea37edf41cb50e899d03baa02bdeecade Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Thu, 31 Oct 2013 08:26:23 -0700 Subject: Add a generic register script handler This is based on the RCBA configuration setup from haswell. It handles PCI, BARs, IO, MMIO, and baytrail-specific IOSF. I did not extend it to handle MSR yet but that would be another potential register type. There are a number of approaches to this kind of thing, but in the end they have a lot of switch statements and a mass of #defines. I'm not particularly set on any of the details so comments welcome. BUG=chrome-os-partner:23635 BRANCH=rambi TEST=emerge-rambi chromeos-coreboot-rambi Change-Id: Ib873936ecf20fc996a8feeb72b9d04ddb523211f Signed-off-by: Duncan Laurie Reviewed-on: https://chromium-review.googlesource.com/175206 Commit-Queue: Aaron Durbin Tested-by: Aaron Durbin Signed-off-by: Aaron Durbin Reviewed-on: http://review.coreboot.org/4923 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc --- src/lib/Makefile.inc | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/lib/Makefile.inc') diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index f2b0fe3297..acd334e25d 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -110,6 +110,8 @@ ramstage-y += cbmem_info.c ramstage-y += hexdump.c romstage-y += hexdump.c +ramstage-$(CONFIG_REG_SCRIPT) += reg_script.c + romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += ramstage_cache.c ifneq ($(CONFIG_HAVE_ARCH_MEMSET),y) -- cgit v1.2.3