From fc19ab5f3465d8f8a861f7492634d0afe847f56d Mon Sep 17 00:00:00 2001 From: Maulik Date: Fri, 5 Jan 2018 22:40:35 +0530 Subject: src/soc/intel: Add new device IDs to support coffeelake 1. Add new device IDs for SATA, GT and Northbridge to pci_ids.h 2. Add entry to identify CFL U GT and CPU to respective files 3. Add entry to identify CFL U to report_platform.c BUG=none BRANCH=none TEST=Boot to CFL U RVP board with this patch and check if coreboot is able to enumerate various devices and display correct component names properly in serial logs. Change-Id: I47c97fb9eb813587cd655e2bce05a686091619ed Signed-off-by: Maulik Reviewed-on: https://review.coreboot.org/27522 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Naresh Solanki Reviewed-by: Subrata Banik --- src/include/device/pci_ids.h | 4 ++++ 1 file changed, 4 insertions(+) (limited to 'src/include') diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index b3a8c574da..c9e4212767 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -2774,6 +2774,8 @@ #define PCI_DEVICE_ID_INTEL_CNL_SATA 0x9dd5 #define PCI_DEVICE_ID_INTEL_CNL_PREMIUM_SATA 0x9dd7 #define PCI_DEVICE_ID_INTEL_CNL_COMPAT_SATA 0x282a +#define PCI_DEVICE_ID_INTEL_CNP_H_SATA 0xa352 +#define PCI_DEVICE_ID_INTEL_CNP_LP_SATA 0x9dd3 /* Intel PMC device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_PMC 0x9d21 @@ -2882,6 +2884,7 @@ #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_2 0x5A5A #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_3 0x5A42 #define PCI_DEVICE_ID_INTEL_CNL_GT2_ULT_4 0x5A4A +#define PCI_DEVICE_ID_INTEL_CFL_GT2_ULT 0x3EA5 /* Intel Northbridge Ids */ #define PCI_DEVICE_ID_INTEL_APL_NB 0x5af0 @@ -2900,6 +2903,7 @@ #define PCI_DEVICE_ID_INTEL_CNL_ID_U 0x5A04 #define PCI_DEVICE_ID_INTEL_CNL_ID_Y 0x5A02 #define PCI_DEVICE_ID_INTEL_WHL_ID_W 0x3E34 +#define PCI_DEVICE_ID_INTEL_CFL_ID_U 0x3ED0 /* Intel SMBUS device Ids */ #define PCI_DEVICE_ID_INTEL_SPT_LP_SMBUS 0x9d23 -- cgit v1.2.3