From ce39ba97bc1906e7fbfec09312fcfec2919cf03e Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= <kyosti.malkki@gmail.com>
Date: Sat, 4 Jan 2020 16:15:50 +0200
Subject: drivers/pc80/rtc: Reorganize prototypes
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Change-Id: Idea18f437c31ebe83dd61a185e614106a1f8f976
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38199
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/include/console/console.h  | 24 ++----------------------
 src/include/pc80/mc146818rtc.h |  1 -
 src/include/post.h             | 28 ++++++++++++++++++++++++++++
 3 files changed, 30 insertions(+), 23 deletions(-)
 create mode 100644 src/include/post.h

(limited to 'src/include')

diff --git a/src/include/console/console.h b/src/include/console/console.h
index 95c0e7fe1a..fdc48da73f 100644
--- a/src/include/console/console.h
+++ b/src/include/console/console.h
@@ -7,6 +7,7 @@
 #include <stdint.h>
 #include <arch/cpu.h>
 #include <console/post_codes.h>
+#include <console/vtxprintf.h>
 
 /* console.h is supposed to provide the log levels defined in here: */
 #include <commonlib/loglevel.h>
@@ -14,31 +15,10 @@
 #define RAM_DEBUG (CONFIG(DEBUG_RAM_SETUP) ? BIOS_DEBUG : BIOS_NEVER)
 #define RAM_SPEW  (CONFIG(DEBUG_RAM_SETUP) ? BIOS_SPEW  : BIOS_NEVER)
 
-#include <console/vtxprintf.h>
-
-struct device;
-
 void post_code(u8 value);
+void mainboard_post(u8 value);
 void arch_post_code(u8 value);
-void cmos_post_code(u8 value);
-void cmos_post_extra(u32 value);
-void cmos_post_path(const struct device *dev);
-int cmos_post_previous_boot(u8 *code, u32 *extra);
-
-static inline void post_log_path(const struct device *dev)
-{
-	if (CONFIG(CMOS_POST) && dev)
-		cmos_post_path(dev);
-}
-
-static inline void post_log_clear(void)
-{
-	if (CONFIG(CMOS_POST))
-		cmos_post_extra(0);
-}
 
-/* this function is weak and can be overridden by a mainboard function. */
-void mainboard_post(u8 value);
 void __noreturn die(const char *fmt, ...);
 #define die_with_post_code(value, fmt, ...) \
 	do { post_code(value); die(fmt, ##__VA_ARGS__); } while (0)
diff --git a/src/include/pc80/mc146818rtc.h b/src/include/pc80/mc146818rtc.h
index 353a09b416..c9e054b048 100644
--- a/src/include/pc80/mc146818rtc.h
+++ b/src/include/pc80/mc146818rtc.h
@@ -183,6 +183,5 @@ void cmos_set_checksum(int range_start, int range_end, int cks_loc);
 
 #endif /* CONFIG_ARCH_X86 */
 
-void cmos_post_init(void);
 
 #endif /*  PC80_MC146818RTC_H */
diff --git a/src/include/post.h b/src/include/post.h
new file mode 100644
index 0000000000..5c1e816ea7
--- /dev/null
+++ b/src/include/post.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/* This file is part of the coreboot project. */
+
+#ifndef __POST_H__
+#define __POST_H__
+
+#include <stdint.h>
+#include <device/device.h>
+
+void cmos_post_init(void);
+void cmos_post_code(u8 value);
+void cmos_post_extra(u32 value);
+void cmos_post_path(const struct device *dev);
+int cmos_post_previous_boot(u8 *code, u32 *extra);
+
+static inline void post_log_path(const struct device *dev)
+{
+	if (CONFIG(CMOS_POST) && dev)
+		cmos_post_path(dev);
+}
+
+static inline void post_log_clear(void)
+{
+	if (CONFIG(CMOS_POST))
+		cmos_post_extra(0);
+}
+
+#endif
-- 
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