From cd7a70f4879ff6e0f3e334ddf1031ccf0c0d31cf Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Sat, 17 Aug 2019 20:51:08 +0300 Subject: soc/intel: Use common romstage code MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to . Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/include/cpu/intel/romstage.h | 14 -------------- 1 file changed, 14 deletions(-) delete mode 100644 src/include/cpu/intel/romstage.h (limited to 'src/include') diff --git a/src/include/cpu/intel/romstage.h b/src/include/cpu/intel/romstage.h deleted file mode 100644 index fd5d7f4e85..0000000000 --- a/src/include/cpu/intel/romstage.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef _CPU_INTEL_ROMSTAGE_H -#define _CPU_INTEL_ROMSTAGE_H - -#include - -void mainboard_romstage_entry(void); - -/* fill_postcar_frame() is called after raminit completes and right before - * calling run_postcar_phase(). Implementation should call postcar_frame_add_mtrr() - * to tag memory ranges as cacheable to speed up execution of postcar and - * early ramstage. */ -void fill_postcar_frame(struct postcar_frame *pcf); - -#endif /* _CPU_INTEL_ROMSTAGE_H */ -- cgit v1.2.3