From cbd4ee73d71648821a268ce5c700236a95ba6125 Mon Sep 17 00:00:00 2001 From: Michael Niewöhner Date: Thu, 15 Oct 2020 16:11:19 +0200 Subject: cpu/intel/common: correct MSR for the Nominal Performance in CPPC MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The "Nominal Performance" is not the same as the "Guaranteed Performance", but is defined as the performance a processor can deliver continously under ideal environmental conditions. According to edk2, this is the "Maximum Non-Turbo Ratio", which needs to be read from MSR_PLATFORM_INFO instead of IA32_HWP_CAPABILITIES. Correct the entry in the CPPC package. Test: dumped SSDT from Supermicro X11SSM-F and checked decompiled version Change-Id: Ic2c27fd3e14af18aa4101c0acd7a5ede15d1f3a9 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/46464 Reviewed-by: Subrata Banik Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- src/include/cpu/intel/msr.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/include') diff --git a/src/include/cpu/intel/msr.h b/src/include/cpu/intel/msr.h index a2165f365a..da0f0bb68d 100644 --- a/src/include/cpu/intel/msr.h +++ b/src/include/cpu/intel/msr.h @@ -12,4 +12,6 @@ #define MSR_PIC_MSG_CONTROL 0x2e #define TPR_UPDATES_DISABLE (1 << 10) +#define MSR_PLATFORM_INFO 0xce + #endif /* CPU_INTEL_MSR_H */ -- cgit v1.2.3