From c1d227d3120470a9e0b0d9d6f58d334782117820 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Thu, 16 Jul 2020 09:03:06 +0530 Subject: soc/intel/common/cpu: Update COS mask calculation for NEM enhanced mode Update the COS mask calculation to accomodate the RW data as per SoC configuration. Currently only one way is allocated for RW data and configured for non-eviction. For earlier platform this served fine, and could accomodate a RW data up to 256Kb. Starting TGL and JSL, the DCACHE_RAM_SIZE is configured for 512Kb, which cannot be mapped to a single way. Hence update the number of ways to be configured for non- eviction as per total LLC size. The total LLC size/ number of ways gives the way size. DCACHE_RAM_SIZE/ way size gives the number of ways that need to be configured for non- eviction, instead of harcoding it to 1. TGL uses MSR IA32_CR_SF_QOS_MASK_1(0x1891) and IA32_CR_SF_QOS_MASK_2(0x1892) as COS mask selection register and hence needs to be progarmmed accordingly. Also JSL and TGL platforms the COS mask selection is mapped to bit 32:33 of MSR IA32_PQR_ASSOC(0xC8F) and need to be updated in edx(maps 63:32) before MSR write instead of eax(maps 31:0). This implementation corrects that as well. BUG=b:149273819 TEST= Boot waddledoo(JSL), hatch(CML), Volteer(TGL)with NEM enhanced CAR configuration. Signed-off-by: Aamir Bohra Change-Id: I54e047161853bfc70516c1d607aa479e68836d04 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43494 Tested-by: build bot (Jenkins) Reviewed-by: Shreesh Chhabbi Reviewed-by: Tim Wawrzynczak --- src/include/cpu/x86/msr.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/include') diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index c761bc04b6..1573eeff7f 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -90,6 +90,9 @@ #define IA32_L3_MASK_1 0xc91 #define IA32_L3_MASK_2 0xc92 +#define IA32_CR_SF_QOS_MASK_1 0x1891 +#define IA32_CR_SF_QOS_MASK_2 0x1892 + #ifndef __ASSEMBLER__ #include -- cgit v1.2.3