From bc8176c5526ec9124aa99559f9432210be364dfe Mon Sep 17 00:00:00 2001 From: Marc Jones Date: Fri, 4 May 2007 18:24:55 +0000 Subject: This patch adds support for the AMD Geode LX CPU. (rediffed) Signed-off-by: Marc Jones Acked-by: Stefan Reinauer git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2628 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1 --- src/include/cpu/amd/geode_post_code.h | 196 +++++++ src/include/cpu/amd/lxdef.h | 1040 +++++++-------------------------- src/include/cpu/amd/vr.h | 52 +- src/include/spd.h | 11 + 4 files changed, 442 insertions(+), 857 deletions(-) create mode 100644 src/include/cpu/amd/geode_post_code.h (limited to 'src/include') diff --git a/src/include/cpu/amd/geode_post_code.h b/src/include/cpu/amd/geode_post_code.h new file mode 100644 index 0000000000..5a0e57689a --- /dev/null +++ b/src/include/cpu/amd/geode_post_code.h @@ -0,0 +1,196 @@ +/* +* This file is part of the LinuxBIOS project. +* +* Copyright (C) 2007 Advanced Micro Devices +* +* This program is free software; you can redistribute it and/or modify +* it under the terms of the GNU General Public License version 2 as +* published by the Free Software Foundation. +* +* This program is distributed in the hope that it will be useful, +* but WITHOUT ANY WARRANTY; without even the implied warranty of +* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +* GNU General Public License for more details. +* +* You should have received a copy of the GNU General Public License +* along with this program; if not, write to the Free Software +* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA +*/ +/* standard AMD post definitions -- might as well use them. */ +#define POST_Output_Port (0x080) /* port to write post codes to*/ + +#define POST_preSioInit (0x000) /* geode.asm*/ +#define POST_clockInit (0x001) /* geode.asm*/ +#define POST_CPURegInit (0x002) /* geode.asm*/ +#define POST_UNREAL (0x003) /* geode.asm*/ +#define POST_CPUMemRegInit (0x004) /* geode.asm*/ +#define POST_CPUTest (0x005) /* geode.asm*/ +#define POST_memSetup (0x006) /* geode.asm*/ +#define POST_memSetUpStack (0x007) /* geode.asm*/ +#define POST_memTest (0x008) /* geode.asm*/ +#define POST_shadowRom (0x009) /* geode.asm*/ +#define POST_memRAMoptimize (0x00A) /* geode.asm*/ +#define POST_cacheInit (0x00B) /* geode.asm*/ +#define POST_northBridgeInit (0x00C) /* geode.asm*/ +#define POST_chipsetInit (0x00D) /* geode.asm*/ +#define POST_sioTest (0x00E) /* geode.asm*/ +#define POST_pcATjunk (0x00F) /* geode.asm*/ + + +#define POST_intTable (0x010) /* geode.asm*/ +#define POST_memInfo (0x011) /* geode.asm*/ +#define POST_romCopy (0x012) /* geode.asm*/ +#define POST_PLLCheck (0x013) /* geode.asm*/ +#define POST_keyboardInit (0x014) /* geode.asm*/ +#define POST_cpuCacheOff (0x015) /* geode.asm*/ +#define POST_BDAInit (0x016) /* geode.asm*/ +#define POST_pciScan (0x017) /* geode.asm*/ +#define POST_optionRomInit (0x018) /* geode.asm*/ +#define POST_ResetLimits (0x019) /* geode.asm*/ +#define POST_summary_screen (0x01A) /* geode.asm*/ +#define POST_Boot (0x01B) /* geode.asm*/ +#define POST_SystemPreInit (0x01C) /* geode.asm*/ +#define POST_ClearRebootFlag (0x01D) /* geode.asm*/ +#define POST_GLIUInit (0x01E) /* geode.asm*/ +#define POST_BootFailed (0x01F) /* geode.asm*/ + + +#define POST_CPU_ID (0x020) /* cpucpuid.asm*/ +#define POST_COUNTERBROKEN (0x021) /* pllinit.asm*/ +#define POST_DIFF_DIMMS (0x022) /* pllinit.asm*/ +#define POST_WIGGLE_MEM_LINES (0x023) /* pllinit.asm*/ +#define POST_NO_GLIU_DESC (0x024) /* pllinit.asm*/ +#define POST_CPU_LCD_CHECK (0x025) /* pllinit.asm*/ +#define POST_CPU_LCD_PASS (0x026) /* pllinit.asm*/ +#define POST_CPU_LCD_FAIL (0x027) /* pllinit.asm*/ +#define POST_CPU_STEPPING (0x028) /* cpucpuid.asm*/ +#define POST_CPU_DM_BIST_FAILURE (0x029) /* gx2reg.asm*/ +#define POST_CPU_FLAGS (0x02A) /* cpucpuid.asm*/ +#define POST_CHIPSET_ID (0x02b) /* chipset.asm*/ +#define POST_CHIPSET_ID_PASS (0x02c) /* chipset.asm*/ +#define POST_CHIPSET_ID_FAIL (0x02d) /* chipset.asm*/ +#define POST_CPU_ID_GOOD (0x02E) /* cpucpuid.asm*/ +#define POST_CPU_ID_FAIL (0x02F) /* cpucpuid.asm*/ + + + +/* PCI config*/ +#define P80_PCICFG (0x030) /* pcispace.asm*/ + + +/* PCI io*/ +#define P80_PCIIO (0x040) /* pcispace.asm*/ + + +/* PCI memory*/ +#define P80_PCIMEM (0x050) /* pcispace.asm*/ + + +/* SIO*/ +#define P80_SIO (0x060) /* *sio.asm*/ + +/* Memory Setp*/ +#define P80_MEM_SETUP (0x070) /* docboot meminit*/ +#define POST_MEM_SETUP (0x070) /* memsize.asm*/ +#define ERROR_32BIT_DIMMS (0x071) /* memsize.asm*/ +#define POST_MEM_SETUP2 (0x072) /* memsize.asm*/ +#define POST_MEM_SETUP3 (0x073) /* memsize.asm*/ +#define POST_MEM_SETUP4 (0x074) /* memsize.asm*/ +#define POST_MEM_SETUP5 (0x075) /* memsize.asm*/ +#define POST_MEM_ENABLE (0x076) /* memsize.asm*/ +#define ERROR_NO_DIMMS (0x077) /* memsize.asm*/ +#define ERROR_DIFF_DIMMS (0x078) /* memsize.asm*/ +#define ERROR_BAD_LATENCY (0x079) /* memsize.asm*/ +#define ERROR_SET_PAGE (0x07a) /* memsize.asm*/ +#define ERROR_DENSITY_DIMM (0x07b) /* memsize.asm*/ +#define ERROR_UNSUPPORTED_DIMM (0x07c) /* memsize.asm*/ +#define ERROR_BANK_SET (0x07d) /* memsize.asm*/ +#define POST_MEM_SETUP_GOOD (0x07E) /* memsize.asm*/ +#define POST_MEM_SETUP_FAIL (0x07F) /* memsize.asm*/ + + +#define POST_UserPreInit (0x080) /* geode.asm*/ +#define POST_UserPostInit (0x081) /* geode.asm*/ +#define POST_Equipment_check (0x082) /* geode.asm*/ +#define POST_InitNVRAMBX (0x083) /* geode.asm*/ +#define POST_NoPIRTable (0x084) /* pci.asm*/ +#define POST_ChipsetFingerPrintPass (0x085) /* prechipsetinit*/ +#define POST_ChipsetFingerPrintFail (0x086) /* prechipsetinit*/ +#define POST_CPU_IM_TAG_BIST_FAILURE (0x087) /* gx2reg.asm*/ +#define POST_CPU_IM_DATA_BIST_FAILURE (0x088) /* gx2reg.asm*/ +#define POST_CPU_FPU_BIST_FAILURE (0x089) /* gx2reg.asm*/ +#define POST_CPU_BTB_BIST_FAILURE (0x08a) /* gx2reg.asm*/ +#define POST_CPU_EX_BIST_FAILURE (0x08b) /* gx2reg.asm*/ +#define POST_Chipset_PI_Test_Fail (0x08c) /* prechipsetinit*/ +#define POST_Chipset_SMBus_SDA_Test_Fail (0x08d) /* prechipsetinit*/ +#define POST_BIT_CLK_Fail (0x08e) /* Hawk geode.asm override*/ + + +#define POST_STACK_SETUP (0x090) /* memstack.asm*/ +#define POST_CPU_PF_BIST_FAILURE (0x091) /* gx2reg.asm*/ +#define POST_CPU_L2_BIST_FAILURE (0x092) /* gx2reg.asm*/ +#define POST_CPU_GLCP_BIST_FAILURE (0x093) /* gx2reg.asm*/ +#define POST_CPU_DF_BIST_FAILURE (0x094) /* gx2reg.asm*/ +#define POST_CPU_VG_BIST_FAILURE (0x095) /* gx2reg.asm*/ +#define POST_CPU_VIP_BIST_FAILURE (0x096) /* gx2reg.asm*/ +#define POST_STACK_SETUP_PASS (0x09E) /* memstack.asm*/ +#define POST_STACK_SETUP_FAIL (0x09F) /* memstack.asm*/ + + +#define POST_PLL_INIT (0x0A0) /* pllinit.asm*/ +#define POST_PLL_MANUAL (0x0A1) /* pllinit.asm*/ +#define POST_PLL_STRAP (0x0A2) /* pllinit.asm*/ +#define POST_PLL_RESET_FAIL (0x0A3) /* pllinit.asm*/ +#define POST_PLL_PCI_FAIL (0x0A4) /* pllinit.asm*/ +#define POST_PLL_MEM_FAIL (0x0A5) /* pllinit.asm*/ +#define POST_PLL_CPU_VER_FAIL (0x0A6) /* pllinit.asm*/ + + +#define POST_MEM_TESTMEM (0x0B0) /* memtest.asm*/ +#define POST_MEM_TESTMEM1 (0x0B1) /* memtest.asm*/ +#define POST_MEM_TESTMEM2 (0x0B2) /* memtest.asm*/ +#define POST_MEM_TESTMEM3 (0x0B3) /* memtest.asm*/ +#define POST_MEM_TESTMEM4 (0x0B4) /* memtest.asm*/ +#define POST_MEM_TESTMEM_PASS (0x0BE) /* memtest.asm*/ +#define POST_MEM_TESTMEM_FAIL (0x0BF) /* memtest.asm*/ + + +#define POST_SECUROM_SECBOOT_START (0x0C0) /* secstart.asm*/ +#define POST_SECUROM_BOOTSRCSETUP (0x0C1) /* secstart.asm*/ +#define POST_SECUROM_REMAP_FAIL (0x0C2) /* secstart.asm*/ +#define POST_SECUROM_BOOTSRCSETUP_FAIL (0x0C3) /* secstart.asm*/ +#define POST_SECUROM_DCACHESETUP (0x0C4) /* secstart.asm*/ +#define POST_SECUROM_DCACHESETUP_FAIL (0x0C5) /* secstart.asm*/ +#define POST_SECUROM_ICACHESETUP (0x0C6) /* secstart.asm*/ +#define POST_SECUROM_DESCRIPTORSETUP (0x0C7) /* secstart.asm*/ +#define POST_SECUROM_DCACHESETUPBIOS (0x0C8) /* secstart.asm*/ +#define POST_SECUROM_PLATFORMSETUP (0x0C9) /* secstart.asm*/ +#define POST_SECUROM_SIGCHECKBIOS (0x0CA) /* secstart.asm*/ +#define POST_SECUROM_ICACHESETUPBIOS (0x0CB) /* secstart.asm*/ +#define POST_SECUROM_PASS (0x0CC) /* secstart.asm*/ +#define POST_SECUROM_FAIL (0x0CD) /* secstart.asm*/ + +#define POST_RCONFInitError (0x0CE) /* cache.asm*/ +#define POST_CacheInitError (0x0CF) /* cache.asm*/ + + +#define POST_ROM_PREUNCOMPRESS (0x0D0) /* rominit.asm*/ +#define POST_ROM_UNCOMPRESS (0x0D1) /* rominit.asm*/ +#define POST_ROM_SMM_INIT (0x0D2) /* rominit.asm*/ +#define POST_ROM_VID_BIOS (0x0D3) /* rominit.asm*/ +#define POST_ROM_LCDINIT (0x0D4) /* rominit.asm*/ +#define POST_ROM_SPLASH (0x0D5) /* rominit.asm*/ +#define POST_ROM_HDDINIT (0x0D6) /* rominit.asm*/ +#define POST_ROM_SYS_INIT (0x0D7) /* rominit.asm*/ +#define POST_ROM_DMM_INIT (0x0D8) /* rominit.asm*/ +#define POST_ROM_TVINIT (0x0D9) /* rominit.asm*/ +#define POST_ROM_POSTUNCOMPRESS (0x0DE) + + +#define P80_CHIPSET_INIT (0x0E0) /* chipset.asm*/ +#define POST_PreChipsetInit (0x0E1) /* geode.asm*/ +#define POST_LateChipsetInit (0x0E2) /* geode.asm*/ +#define POST_NORTHB_INIT (0x0E8) /* northb.asm*/ + + +#define POST_INTR_SEG_JUMP (0x0F0) /* vector.asm*/ diff --git a/src/include/cpu/amd/lxdef.h b/src/include/cpu/amd/lxdef.h index 6d5f412241..fbe7b6edae 100644 --- a/src/include/cpu/amd/lxdef.h +++ b/src/include/cpu/amd/lxdef.h @@ -24,42 +24,21 @@ #ifndef CPU_AMD_LXDEF_H #define CPU_AMD_LXDEF_H -#define CPU_ID_1_X 0x540 /* Stepping ID 1.x*/ -#define CPU_ID_2_0 0x551 /* Stepping ID 2.0*/ -#define CPU_ID_2_1 0x552 /* Stepping ID 2.1*/ -#define CPU_ID_2_2 0x553 /* Stepping ID 2.2*/ - -#define CPU_REV_1_0 0x011 -#define CPU_REV_1_1 0x012 -#define CPU_REV_1_2 0x013 -#define CPU_REV_1_3 0x014 + +#define CPU_ID_1_X 0x00000560 /* Stepping ID 1.x CPUbug fix to change it to 5A0*/ +#define CPU_ID_2_0 0x000005A1 +#define CPU_ID_3_0 0x000005A2 + +#define CPU_REV_1_0 0x010 +#define CPU_REV_1_1 0x011 #define CPU_REV_2_0 0x020 #define CPU_REV_2_1 0x021 #define CPU_REV_2_2 0x022 -#define CPU_REV_3_0 0x030 -/* GeodeLink Control Processor Registers, GLIU1, Port 3 */ -#define GLCP_CLK_DIS_DELAY 0x4c000008 -#define GLCP_PMCLKDISABLE 0x4c000009 -#define GLCP_CHIP_REVID 0x4c000017 - -/* GLCP_SYS_RSTPLL, Upper 32 bits */ -#define GLCP_SYS_RSTPLL_MDIV_SHIFT 9 -#define GLCP_SYS_RSTPLL_VDIV_SHIFT 6 -#define GLCP_SYS_RSTPLL_FBDIV_SHIFT 0 - -/* GLCP_SYS_RSTPLL, Lower 32 bits */ -#define GLCP_SYS_RSTPLL_SWFLAGS_SHIFT 26 -#define GLCP_SYS_RSTPLL_SWFLAGS_MASK (0x3f << 26) - -#define GLCP_SYS_RSTPLL_LOCKWAIT 24 -#define GLCP_SYS_RSTPLL_HOLDCOUNT 16 -#define GLCP_SYS_RSTPLL_BYPASS 15 -#define GLCP_SYS_RSTPLL_PD 14 -#define GLCP_SYS_RSTPLL_RESETPLL 13 -#define GLCP_SYS_RSTPLL_DDRMODE 10 -#define GLCP_SYS_RSTPLL_VA_SEMI_SYNC_MODE 9 -#define GLCP_SYS_RSTPLL_PCI_SEMI_SYNC_MODE 8 -#define GLCP_SYS_RSTPLL_CHIP_RESET 0 +#define CPU_REV_C_0 0x030 +#define CPU_REV_C_1 0x031 +#define CPU_REV_C_2 0x032 /* 3.2 part was never produced ...*/ +#define CPU_REV_C_3 0x033 + /* MSR routing as follows*/ /* MSB = 1 means not for CPU*/ @@ -67,80 +46,57 @@ /* next3 bits next port if through an GLIU*/ /* etc...*/ -/*Redcloud as follows.*/ -/* GLIU0*/ -/* port0 - GLIU0*/ -/* port1 - MC*/ -/* port2 - GLIU1*/ -/* port3 - CPU*/ -/* port4 - VG*/ -/* port5 - GP*/ -/* port6 - DF*/ - -/* GLIU1*/ -/* port1 - GLIU0*/ -/* port3 - GLCP*/ -/* port4 - PCI*/ -/* port5 - FG*/ - - -/* start GX3 def, differences are marked with GX3 comment */ - +/* GLIU0 ports */ #define GL0_GLIU0 0 #define GL0_MC 1 #define GL0_GLIU1 2 #define GL0_CPU 3 #define GL0_VG 4 #define GL0_GP 5 -//#define GL0_DF 6 //GX3 no such thing as VP port +/* GLIU1 ports */ #define GL1_GLIU0 1 -//GX3 VP port #define GL1_DF 2 #define GL1_GLCP 3 #define GL1_PCI 4 #define GL1_VIP 5 #define GL1_AES 6 -#define MSR_GLIU0 (GL0_GLIU0 << 29) + (1 << 28) /* 1000xxxx - To get on GeodeLink one bit has to be set */ + +#define MSR_GLIU0 (GL0_GLIU0 << 29) + (1 << 28) /* 1000xxxx, To get on GeodeLink one bit has to be set */ #define MSR_MC (GL0_MC << 29) /* 2000xxxx */ #define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */ -#define MSR_CPU (GL0_CPU << 32) /* 0000xxxx - this is not used for BIOS */ //GX3 +#define MSR_CPU (GL0_CPU << 29) /* 0000xxxx this is not used for BIOS since code executing on CPU doesn't need to be routed*/ #define MSR_VG (GL0_VG << 29) /* 8000xxxx */ #define MSR_GP (GL0_GP << 29) /* A000xxxx */ -//#define MSR_DF (GL0_DF << 29) /* C000xxxx */ //GX3 no such thing -#define MSR_GLCP (GL1_GLCP << 26) + MSR_GLIU1 /* 4C00xxxx */ -#define MSR_PCI (GL1_PCI << 26) + MSR_GLIU1 /* 5000xxxx */ -//#define MSR_FG (GL1_FG << 26) + MSR_GLIU1 /* 5400xxxx */ //GX3: no such thing +#define MSR_DF ((GL1_DF << 26) + MSR_GLIU1) /* 4800xxxx */ +#define MSR_GLCP ((GL1_GLCP << 26) + MSR_GLIU1) /* 4C00xxxx */ +#define MSR_PCI ((GL1_PCI << 26) + MSR_GLIU1) /* 5000xxxx */ #define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1) /* 5400xxxx */ #define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) /* 5800xxxx */ -/* South Bridge*/ -#define SB_PORT 2 /* port of the SouthBridge */ -#define MSR_SB ((SB_PORT << 23) + MSR_PCI) /* 5100xxxx - address to the SouthBridge*/ -#define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift.*/ +#define MSR_FG MSR_GLCP - -/**/ /*GeodeLink Interface Unit 0 (GLIU0) port0*/ -/**/ #define GLIU0_GLD_MSR_CAP (MSR_GLIU0 + 0x2000) +#define GLIU0_GLD_MSR_ERROR (MSR_GLIU0 + 0x2003) #define GLIU0_GLD_MSR_PM (MSR_GLIU0 + 0x2004) #define GLIU0_DESC_BASE (MSR_GLIU0 + 0x20) #define GLIU0_CAP (MSR_GLIU0 + 0x86) #define GLIU0_GLD_MSR_COH (MSR_GLIU0 + 0x80) +#define GLIU0_ARB (MSR_GLIU0 + 0x82) +#define ARB_UPPER_QUACK_EN_SET (1 << 31) +#define ARB_UPPER_DACK_EN_SET (1 << 28) -/**/ /* Memory Controller GLIU0 port 1*/ -/**/ + #define MC_GLD_MSR_CAP (MSR_MC + 0x2000) #define MC_GLD_MSR_PM (MSR_MC + 0x2004) #define MC_CF07_DATA (MSR_MC + 0x18) - #define CF07_UPPER_D1_SZ_SHIFT 28 #define CF07_UPPER_D1_MB_SHIFT 24 #define CF07_UPPER_D1_CB_SHIFT 20 @@ -160,52 +116,56 @@ #define MC_CF8F_DATA (MSR_MC + 0x19) - #define CF8F_UPPER_XOR_BS_SHIFT 19 #define CF8F_UPPER_XOR_MB0_SHIFT 18 #define CF8F_UPPER_XOR_BA1_SHIFT 17 #define CF8F_UPPER_XOR_BA0_SHIFT 16 #define CF8F_UPPER_REORDER_DIS_SET (1 << 8) -#define CF8F_UPPER_REG_DIMM_SHIFT 4 #define CF8F_LOWER_CAS_LAT_SHIFT 28 -#define CF8F_LOWER_REF2ACT_SHIFT 24 +#define CF8F_LOWER_ACT2ACTREF_SHIFT 24 #define CF8F_LOWER_ACT2PRE_SHIFT 20 #define CF8F_LOWER_PRE2ACT_SHIFT 16 #define CF8F_LOWER_ACT2CMD_SHIFT 12 #define CF8F_LOWER_ACT2ACT_SHIFT 8 -#define CF8F_UPPER_32BIT_SET (1 << 5) #define CF8F_UPPER_HOI_LOI_SET (1 << 1) #define MC_CF1017_DATA (MSR_MC + 0x1A) - +#define CF1017_LOWER_WR_TO_RD_SHIFT 28 +#define CF1017_LOWER_RD_TMG_CTL_SHIFT 24 +#define CF1017_LOWER_REF2ACT_SHIFT 16 #define CF1017_LOWER_PM1_UP_DLY_SET (1 << 8) #define CF1017_LOWER_WR2DAT_SHIFT 0 #define MC_CFCLK_DBUG (MSR_MC + 0x1D) #define CFCLK_UPPER_MTST_B2B_DIS_SET (1 << 2) -#define CFCLK_UPPER_MTST_DQS_EN_SET (1 << 1) +#define CFCLK_UPPER_MTST_RBEX_EN_SET (1 << 1) #define CFCLK_UPPER_MTEST_EN_SET (1 << 0) +#define CFCLK_LOWER_FORCE_PRE_SET (1 << 16) +#define CFCLK_LOWER_TRISTATE_DIS_SET (1 << 12) #define CFCLK_LOWER_MASK_CKE_SET1 (1 << 9) #define CFCLK_LOWER_MASK_CKE_SET0 (1 << 8) #define CFCLK_LOWER_SDCLK_SET (0x0F << 0) #define MC_CF_RDSYNC (MSR_MC + 0x1F) +#define MC_CF_PMCTR (MSR_MC + 0x20) -/**/ /* GLIU1 GLIU0 port2*/ -/**/ + #define GLIU1_GLD_MSR_CAP (MSR_GLIU1 + 0x2000) +#define GLIU1_GLD_MSR_ERROR (MSR_GLIU1 + 0x2003) #define GLIU1_GLD_MSR_PM (MSR_GLIU1 + 0x2004) #define GLIU1_GLD_MSR_COH (MSR_GLIU1 + 0x80) +#define GLIU1_PORT_ACTIVE (MSR_GLIU1 + 0x81) +#define GLIU1_ARB (MSR_GLIU1 + 0x82) + -/**/ /* CPU ; does not need routing instructions since we are executing there.*/ -/**/ + #define CPU_GLD_MSR_CAP 0x2000 #define CPU_GLD_MSR_CONFIG 0x2001 #define CPU_GLD_MSR_PM 0x2004 @@ -216,22 +176,41 @@ #define DIAG_SEL0__MODE_SHIFT 0 #define DIAG_SET0_SET (1 << 15) -#define CPU_PF_BTB_CONF 0x1100 -#define BTB_ENABLE_SET (1 << 0) +#define CPU_PF_CONF 0x1100 #define RETURN_STACK_ENABLE_SET (1 << 4) -#define CPU_PF_BTBRMA_BIST 0x110C +#define PF_CONF_CC_L1 (1 << 0) +#define CPU_PF_INVD 0x1102 +#define PF_RS_INVD_SET (1 << 1) +#define PF_CC_INVD_SET (1 << 0) +#define CPU_PF_BIST 0x1140 #define CPU_XC_CONFIG 0x1210 #define XC_CONFIG_SUSP_ON_HLT (1 << 0) +#define XC_CONFIG_SUSP_ON_PAUSE (1 << 1) + #define CPU_ID_CONFIG 0x1250 #define ID_CONFIG_SERIAL_SET (1 << 0) #define CPU_AC_MSR 0x1301 + +/* SMM*/ +#define CPU_AC_SMM_CTL 0x1301 +#define SMM_NMI_EN_SET (1 << 0) +#define SMM_SUSP_EN_SET (1 << 1) +#define NEST_SMI_EN_SET (1 << 2) +#define SMM_INST_EN_SET (1 << 3) +#define INTL_SMI_EN_SET (1 << 4) +#define EXTL_SMI_EN_SET (1 << 5) + #define CPU_EX_BIST 0x1428 /*IM*/ #define CPU_IM_CONFIG 0x1700 +#define IM_CONFIG_LOWER_SERIAL_SET (1 << 2) +#define IM_CONFIG_LOWER_L0WE_SET (1 << 6) #define IM_CONFIG_LOWER_ICD_SET (1 << 8) +#define IM_CONFIG_LOWER_EBE_SET (1 << 10) +#define IM_CONFIG_LOWER_ABSE_SET (1 << 11) #define IM_CONFIG_LOWER_QWT_SET (1 << 20) #define CPU_IC_INDEX 0x1710 #define CPU_IC_DATA 0x1711 @@ -245,20 +224,14 @@ #define CPU_IM_BIST_DATA 0x1731 -/* ----- GX3 OK ---- */ - -/* various CPU MSRs */ +/*DM MSR MAP*/ #define CPU_DM_CONFIG0 0x1800 #define DM_CONFIG0_UPPER_WSREQ_SHIFT 12 -#define DM_CONFIG0_LOWER_DCDIS_SET (1<<8) +#define DM_CONFIG0_LOWER_EVCTONRPL_SET (1 << 14) #define DM_CONFIG0_LOWER_WBINVD_SET (1<<5) +#define DM_CONFIG0_LOWER_DCDIS_SET (1 << 8) #define DM_CONFIG0_LOWER_MISSER_SET (1<<1) -#define CPU_DM_CONFIG1 0x1801 - -#define CPU_DM_PFLOCK 0x1804 - -/* configuration MSRs */ #define CPU_RCONF_DEFAULT 0x1808 #define RCONF_DEFAULT_UPPER_ROMRC_SHIFT 24 #define RCONF_DEFAULT_UPPER_ROMBASE_SHIFT 4 @@ -267,16 +240,11 @@ #define RCONF_DEFAULT_LOWER_SYSTOP_SHIFT 8 #define RCONF_DEFAULT_LOWER_SYSRC_SHIFT 0 - #define CPU_RCONF_BYPASS 0x180A #define CPU_RCONF_A0_BF 0x180B #define CPU_RCONF_C0_DF 0x180C #define CPU_RCONF_E0_FF 0x180D -/* ------------------------ */ - -/* ----- GX3 OK ---- */ - #define CPU_RCONF_SMM 0x180E #define RCONF_SMM_UPPER_SMMTOP_SHIFT 12 #define RCONF_SMM_UPPER_RCSMM_SHIFT 0 @@ -284,9 +252,6 @@ #define RCONF_SMM_LOWER_RCNORM_SHIFT 0 #define RCONF_SMM_LOWER_EN_SET (1<<8) -/* ------------------------ */ - - #define CPU_RCONF_DMM 0x180F #define RCONF_DMM_UPPER_DMMTOP_SHIFT 12 #define RCONF_DMM_UPPER_RCDMM_SHIFT 0 @@ -294,10 +259,6 @@ #define RCONF_DMM_LOWER_RCNORM_SHIFT 0 #define RCONF_DMM_LOWER_EN_SET (1<<8) - - -/* ----- GX3 OK ---- */ - #define CPU_RCONF0 0x1810 #define CPU_RCONF1 0x1811 #define CPU_RCONF2 0x1812 @@ -306,20 +267,10 @@ #define CPU_RCONF5 0x1815 #define CPU_RCONF6 0x1816 #define CPU_RCONF7 0x1817 - -/* ------------------------ */ - -/* ----- GX3 OK ---- */ - #define CPU_CR1_MSR 0x1881 #define CPU_CR2_MSR 0x1882 #define CPU_CR3_MSR 0x1883 #define CPU_CR4_MSR 0x1884 - -/* ------------------------ */ - -/* ----- GX3 OK ---- */ - #define CPU_DC_INDEX 0x1890 #define CPU_DC_DATA 0x1891 #define CPU_DC_TAG 0x1892 @@ -329,48 +280,83 @@ #define CPU_DTB_LRU 0x1899 #define CPU_DTB_ENTRY 0x189A #define CPU_DTB_ENTRY_I 0x189B - -/* ------------------------ */ - #define CPU_L2TB_INDEX 0x189C #define CPU_L2TB_LRU 0x189D #define CPU_L2TB_ENTRY 0x189E #define CPU_L2TB_ENTRY_I 0x189F #define CPU_DM_BIST 0x18C0 - /* SMM*/ -#define CPU_AC_SMM_CTL 0x1301 -#define SMM_NMI_EN_SET (1<<0) -#define SMM_SUSP_EN_SET (1<<1) -#define NEST_SMI_EN_SET (1<<2) -#define SMM_INST_EN_SET (1<<3) -#define INTL_SMI_EN_SET (1<<4) -#define EXTL_SMI_EN_SET (1<<5) - -#define CPU_FPU_MSR_MODE 0x1A00 -#define FPU_IE_SET (1<<0) - -#define CPU_FP_UROM_BIST 0x1A03 #define CPU_BC_CONF_0 0x1900 #define TSC_SUSP_SET (1<<5) #define SUSP_EN_SET (1<<12) -/* L2 cache*/ - -#define L2_CONFIG_MSR 0x1920 -#define L2_STATUS_MSR 0x1921 -#define L2_BIST_MSR 0x1926 +#define CPU_BC_CONF_1 0x1901 +#define CPU_BC_MSR_LOCK 0x1908 +#define CPU_BC_L2_CONF 0x1920 +#define BC_L2_ENABLE_SET (1 << 0) +#define BC_L2_ALLOC_ENABLE_SET (1 << 1) +#define BC_L2_DM_ALLOC_ENABLE_SET (1 << 2) +#define BC_L2_IM_ALLOC_ENABLE_SET (1 << 3) +#define BC_L2_INVALIDATE_SET (1 << 4) +#define CPU_BC_L2_STATUS 0x1921 +#define CPU_BC_L2_INDEX 0x1922 +#define CPU_BC_L2_DATA 0x1923 +#define CPU_BC_L2_TAG 0x1924 +#define CPU_BC_L2_TAG_AUTOINC 0x1925 +#define CPU_BC_L2_BIST 0x1926 +#define BC_L2_BIST_TAG_ENABLE_SET (1 << 0) +#define BC_L2_BIST_TAG_DRT_EN_SET (1 << 1) +#define BC_L2_BIST_DATA_ENABLE_SET (1 << 2) +#define BC_L2_BIST_DATA_DRT_EN_SET (1 << 3) +#define BC_L2_BIST_MRU_ENABLE_SET (1 << 4) +#define BC_L2_BIST_MRU_DRT_EN_SET (1 << 5) +#define CPU_BC_PMODE_MSR 0x1930 +#define CPU_BC_MSS_ARRAY_CTL_ENA 0x1980 +#define CPU_BC_MSS_ARRAY_CTL0 0x1981 +#define CPU_BC_MSS_ARRAY_CTL1 0x1982 +#define CPU_BC_MSS_ARRAY_CTL2 0x1983 + +#define CPU_FPU_MSR_MODE 0x1A00 +#define FPU_IE_SET (1 << 0) + +#define CPU_FP_UROM_BIST 0x1A03 + +#define CPU_CPUID0 0x3000 +#define CPU_CPUID1 0x3001 +#define CPU_CPUID2 0x3002 +#define CPU_CPUID3 0x3003 +#define CPU_CPUID4 0x3004 +#define CPU_CPUID5 0x3005 +#define CPU_CPUID6 0x3006 +#define CPU_CPUID7 0x3007 +#define CPU_CPUID8 0x3008 +#define CPU_CPUID9 0x3009 +#define CPU_CPUIDA 0x300A +#define CPU_CPUIDB 0x300B +#define CPU_CPUIDC 0x300C +#define CPU_CPUIDD 0x300D +#define CPU_CPUIDE 0x300E +#define CPU_CPUIDF 0x300F +#define CPU_CPUID10 0x3010 +#define CPU_CPUID11 0x3011 +#define CPU_CPUID12 0x3012 +#define CPU_CPUID13 0x3013 + - - /**/ /* VG GLIU0 port4*/ - /**/ + #define VG_GLD_MSR_CAP (MSR_VG + 0x2000) #define VG_GLD_MSR_CONFIG (MSR_VG + 0x2001) #define VG_GLD_MSR_PM (MSR_VG + 0x2004) +#define VG_BIST (MSR_VG + 0x2010) + + + +/* GP GLIU0 port5*/ + #define GP_GLD_MSR_CAP (MSR_GP + 0x2000) #define GP_GLD_MSR_CONFIG (MSR_GP + 0x2001) @@ -378,57 +364,64 @@ -/**/ /* DF GLIU0 port6*/ -/**/ -/* + + #define DF_GLD_MSR_CAP (MSR_DF + 0x2000) #define DF_GLD_MSR_MASTER_CONF (MSR_DF + 0x2001) #define DF_LOWER_LCD_SHIFT 6 #define DF_GLD_MSR_PM (MSR_DF + 0x2004) +#define DF_BIST (MSR_DF + 0x2005) + -*/ -/**/ /* GeodeLink Control Processor GLIU1 port3*/ -/**/ + #define GLCP_GLD_MSR_CAP (MSR_GLCP + 0x2000) #define GLCP_GLD_MSR_CONF (MSR_GLCP + 0x2001) +#define GLCP_GLD_MSR_SMI (MSR_GLCP + 0x2002) +#define GLCP_GLD_MSR_ERROR (MSR_GLCP + 0x2003) #define GLCP_GLD_MSR_PM (MSR_GLCP + 0x2004) #define GLCP_DELAY_CONTROLS (MSR_GLCP + 0x0F) - -#define GLCP_SYS_RSTPLL (MSR_GLCP +0x14 /* R/W*/) -#define RSTPLL_UPPER_MDIV_SHIFT 9 -#define RSTPLL_UPPER_VDIV_SHIFT 6 -#define RSTPLL_UPPER_FBDIV_SHIFT 0 - +#define GLCP_SYS_RSTPLL (MSR_GLCP + 0x14) /* R/W */ +#define RSTPLL_UPPER_GLMULT_SHIFT 7 +#define RSTPLL_UPPER_GLDIV_SHIFT 6 +#define RSTPLL_UPPER_CPUMULT_SHIFT 1 +#define RSTPLL_UPPER_CPUDIV_SHIFT 0 #define RSTPLL_LOWER_SWFLAGS_SHIFT 26 -#define RSTPLL_LOWER_SWFLAGS_MASK (0x3F< - * Copyright (C) 2003-2005 Advanced Micro Devices, Inc. All Rights Reserved. - * */ -// -//$Id: //bios/main/vsa_ii/inc/vr.h#18 $ -//$Header: //bios/main/vsa_ii/inc/vr.h#18 $ -//$Date: 2005/09/29 $ -//$DateTime: 2005/09/29 11:07:14 $ -//$Change: 65425 $ -//$File: //bios/main/vsa_ii/inc/vr.h $ -//$Revision: #18 $ -//$Author: johnk $ -// -// -// Virtual Register USAGE: -// -// Index: AH = Class, AL = Parameter_ID -// Data: AX = data -// +/* +* +* Copyright (C) 2007 Advanced Micro Devices +* +*/ + +#ifndef CPU_AMD_VR_H +#define CPU_AMD_VR_H #define VRC_INDEX 0xAC1C // Index register #define VRC_DATA 0xAC1E // Data register @@ -484,3 +473,28 @@ #define MAX_THERMAL VRC_THERMAL_SMB_DATA #define MAX_VR_CLASS VRC_THERMAL + +/* + * Write to a Virtual Register + * AX = Class/Index + * CX = data to write + */ +static inline void vrWrite(uint16_t wClassIndex, uint16_t wData) +{ + outl(((uint32_t) VR_UNLOCK << 16) | wClassIndex, VRC_INDEX); + outw(wData, VRC_DATA); +} + + /* + * Read from a Virtual Register + * AX = Class/Index + * Returns a 16-bit word of data + */ +static inline uint16_t vrRead(uint16_t wClassIndex) +{ + uint16_t wData; + outl(((uint32_t) VR_UNLOCK << 16) | wClassIndex, VRC_INDEX); + wData = inw(VRC_DATA); + return wData; +} +#endif diff --git a/src/include/spd.h b/src/include/spd.h index 6703ef2845..b0c00ff094 100644 --- a/src/include/spd.h +++ b/src/include/spd.h @@ -85,6 +85,17 @@ #define SPD_INTEL_SPEC_FOR_FREQUENCY 126 /* Intel specification for frequency */ #define SPD_INTEL_SPEC_100_MHZ 127 /* Intel specification details for 100MHz support */ +/* DRAM specifications use the following naming conventions for SPD locations */ +#define SPD_tRP SPD_MIN_ROW_PRECHARGE_TIME +#define SPD_tRRD SPD_MIN_ROWACTIVE_TO_ROWACTIVE +#define SPD_tRCD SPD_MIN_RAS_TO_CAS_DELAY +#define SPD_tRAS SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY +#define SPD_BANK_DENSITY SPD_DENSITY_OF_EACH_ROW_ON_MODULE +#define SPD_ADDRESS_CMD_HOLD SPD_CMD_SIGNAL_INPUT_HOLD_TIME +#define SPD_tRC 41 /* SDRAM Device Minimum Active to Active/Auto Refresh Time (tRC) */ +#define SPD_tRFC 42 /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh (tRFC) */ + + /* SPD_MEMORY_TYPE values. */ #define SPD_MEMORY_TYPE_FPM_DRAM 1 #define SPD_MEMORY_TYPE_EDO 2 -- cgit v1.2.3