From aa8d7721d400c20b73a1de8036d45654bdc625ee Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Mon, 2 Sep 2019 15:01:56 +0800 Subject: lib/spd_bin: Extend DDR4 spd information From DDR4 SPD spec: Byte 4 (0x004): SDRAM Density and Banks Bits [7, 6]: 00 = 0 (no bank groups) 01 = 1 (2 bank groups) 10 = 2 (4 bank groups) 11 = reserved Bit [5, 4] : 00 = 2 (4 banks) 01 = 3 (8 banks) All others reserved Separate DDR3 and DDR4 banks. And extened capmb, rows, cols and ranks. Separate DDR3 and DDR4 ORGANIZATION/BUS_DEV_WIDTH offset. Signed-off-by: Eric Lai Change-Id: I5f56975ce73d8ed2d4de7d9fd08e5ae86993e731 Reviewed-on: https://review.coreboot.org/c/coreboot/+/35206 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/include/spd_bin.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) (limited to 'src/include') diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index e0a50ff45b..3de60a95ce 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -31,8 +31,10 @@ #define SPD_DRAM_DDR4 0x0C #define SPD_DENSITY_BANKS 4 #define SPD_ADDRESSING 5 -#define SPD_ORGANIZATION 7 -#define SPD_BUS_DEV_WIDTH 8 +#define DDR3_ORGANIZATION 7 +#define DDR3_BUS_DEV_WIDTH 8 +#define DDR4_ORGANIZATION 12 +#define DDR4_BUS_DEV_WIDTH 13 #define DDR3_SPD_PART_OFF 128 #define DDR3_SPD_PART_LEN 18 #define LPDDR3_SPD_PART_OFF 128 -- cgit v1.2.3