From 85a09ef99b56ec4e7398efd1d72b388d92435286 Mon Sep 17 00:00:00 2001 From: Maulik V Vaghela Date: Mon, 21 Mar 2022 14:06:44 +0530 Subject: soc/intel/adl-n: Add device ID for TCSS XHCI This patch adds TCSS XHCI device ID for ADL-N CPU which is required for USB3 port enumeration. Document Reference: 645548 revision 1.0 (Chapter 2.3) BUG=None BRANCH=None TEST=Check if device is detected correctly and ACPI entries are generated for device 0d.0 Change-Id: Id5d42d60eb05137406ef45b9e87e27948fc3b674 Signed-off-by: Maulik V Vaghela Reviewed-on: https://review.coreboot.org/c/coreboot/+/62955 Tested-by: build bot (Jenkins) Reviewed-by: Krishna P Bhat D Reviewed-by: Kangheui Won Reviewed-by: Subrata Banik --- src/include/device/pci_ids.h | 1 + 1 file changed, 1 insertion(+) (limited to 'src/include') diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index d1365f4ac7..ff7d69ad0a 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -4131,6 +4131,7 @@ #define PCI_DID_INTEL_ADP_P_XHCI 0x51ed #define PCI_DID_INTEL_ADP_S_XHCI 0x7ae0 #define PCI_DID_INTEL_ADP_TCSS_XHCI 0x461e +#define PCI_DID_INTEL_ADP_N_TCSS_XHCI 0x464e #define PCI_DID_INTEL_ADP_M_XHCI 0x54ed #define PCI_DID_INTEL_MTL_XHCI 0x7e7d #define PCI_DID_INTEL_MTL_M_TCSS_XHCI 0x7eb0 -- cgit v1.2.3