From 6a8ce0d250f4dbaa2f253e566cf76e20f753d131 Mon Sep 17 00:00:00 2001 From: Kyösti Mälkki Date: Thu, 17 May 2018 17:22:51 +0300 Subject: cpu/intel/car: Prepare for some POSTCAR_STAGE support MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The file cache_as_ram_ht.inc is used across a variety of CPUs and northbridges. We need to split it anyway for future C_ENVIRONMENT_BOOTBLOCK and verstage work. Split and rename the files, remove code that is globally implemented in POSTCAR_STAGE framework already. Change-Id: I2ba67772328fce3d5d1ae34c36aea8dcdcc56b87 Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/26747 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Aaron Durbin --- src/include/cpu/intel/romstage.h | 2 ++ 1 file changed, 2 insertions(+) (limited to 'src/include') diff --git a/src/include/cpu/intel/romstage.h b/src/include/cpu/intel/romstage.h index 3a9e98934b..eace57e558 100644 --- a/src/include/cpu/intel/romstage.h +++ b/src/include/cpu/intel/romstage.h @@ -22,6 +22,8 @@ void mainboard_romstage_entry(unsigned long bist); */ void *setup_stack_and_mtrrs(void); +void platform_enter_postcar(void); + /* romstage_main is called from the cache-as-ram assembly file to prepare * CAR stack guards.*/ asmlinkage void *romstage_main(unsigned long bist); -- cgit v1.2.3