From 62669a24eaf5236a60eebf8e26eefc984ca321ee Mon Sep 17 00:00:00 2001
From: Tim Wawrzynczak <twawrzynczak@chromium.org>
Date: Tue, 1 Sep 2020 16:08:02 -0600
Subject: cpu/x86: Add definition for SMRR_PHYS_MASK_LOCK

The IA32_SMRR_PHYS_MASK MSR contains a 'Lock' bit, which will cause the
core to generate a #GP if the SMRR_BASE or SMRR_MASK registers are
written to after the Lock bit is set; this is helpful with securing SMM.

BUG=b:164489598

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I784d1d1abec0a0fe0ee267118d084ac594a51647
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44991
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
---
 src/include/cpu/x86/mtrr.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'src/include')

diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h
index 42964b02ea..6e30199c5f 100644
--- a/src/include/cpu/x86/mtrr.h
+++ b/src/include/cpu/x86/mtrr.h
@@ -30,6 +30,7 @@
 
 #define IA32_SMRR_PHYS_BASE		0x1f2
 #define IA32_SMRR_PHYS_MASK		0x1f3
+#define SMRR_PHYS_MASK_LOCK		(1 << 10)
 
 /* Specific to model_6fx and model_1067x */
 #define MSR_SMRR_PHYS_BASE		0xa0
-- 
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