From 419bfbc1f1e7bb40c1e5698e1f50d4e275665d97 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 1 Oct 2018 08:47:51 +0200 Subject: src: Move common IA-32 MSRs to Use "cpu/x86/msr.h" for common IA-32 MSRs and correct IA-32 MSRs names. Change-Id: Ida7f2d608c55796abf9452f190a58802e498302d Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/28752 Reviewed-by: Martin Roth Reviewed-by: Lijian Zhao Reviewed-by: Pratikkumar V Prajapati Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- src/include/cpu/intel/l2_cache.h | 1 - src/include/cpu/intel/speedstep.h | 6 +---- src/include/cpu/intel/turbo.h | 1 - src/include/cpu/x86/msr.h | 48 +++++++++++++++++++++++++++++++-------- 4 files changed, 40 insertions(+), 16 deletions(-) (limited to 'src/include') diff --git a/src/include/cpu/intel/l2_cache.h b/src/include/cpu/intel/l2_cache.h index 35059ff74f..1303148025 100644 --- a/src/include/cpu/intel/l2_cache.h +++ b/src/include/cpu/intel/l2_cache.h @@ -27,7 +27,6 @@ #ifndef __P6_L2_CACHE_H #define __P6_L2_CACHE_H -#define IA32_PLATFORM_ID 0x17 #define EBL_CR_POWERON 0x2A #define BBL_CR_D0 0x88 diff --git a/src/include/cpu/intel/speedstep.h b/src/include/cpu/intel/speedstep.h index 5390781304..05d83ed341 100644 --- a/src/include/cpu/intel/speedstep.h +++ b/src/include/cpu/intel/speedstep.h @@ -35,11 +35,7 @@ /* Speedstep related MSRs */ -#define IA32_PLATFORM_ID 0x017 -#define IA32_PERF_STATUS 0x198 -#define IA32_PERF_CTL 0x199 -#define MSR_THERM2_CTL 0x19D -#define IA32_MISC_ENABLES 0x1A0 +#define MSR_THERM2_CTL 0x19D #define MSR_EBC_FREQUENCY_ID 0x2c #define MSR_FSB_FREQ 0xcd #define MSR_FSB_CLOCK_VCC 0xce diff --git a/src/include/cpu/intel/turbo.h b/src/include/cpu/intel/turbo.h index 58f4831d4b..0880ebb07d 100644 --- a/src/include/cpu/intel/turbo.h +++ b/src/include/cpu/intel/turbo.h @@ -20,7 +20,6 @@ #define CPUID_LEAF_PM 6 #define PM_CAP_TURBO_MODE (1 << 1) -#define MSR_IA32_MISC_ENABLES 0x1a0 /* Disable the Monitor Mwait FSM feature */ #define MONITOR_MWAIT_DIS_MASK 0x40000 diff --git a/src/include/cpu/x86/msr.h b/src/include/cpu/x86/msr.h index 85e2131e43..62e56b7a28 100644 --- a/src/include/cpu/x86/msr.h +++ b/src/include/cpu/x86/msr.h @@ -11,14 +11,44 @@ #define EFER_SCE (1 << 0) /* Page attribute type MSR */ -#define MSR_IA32_PAT 0x277 -#define MSR_IA32_MPERF 0xe7 -#define MSR_IA32_APERF 0xe8 -#define MSR_IA32_PM_ENABLE 0x770 -#define MSR_IA32_HWP_CAPABILITIES 0x771 -#define MSR_IA32_HWP_REQUEST 0x774 -#define MSR_IA32_HWP_STATUS 0x777 - +#define IA32_PLATFORM_ID 0x17 +#define IA32_FEATURE_CONTROL 0x3a +#define FEATURE_CONTROL_LOCK_BIT (1 << 0) +#define FEATURE_ENABLE_VMX (1 << 2) +#define SMRR_ENABLE (1 << 3) +#define CPUID_VMX (1 << 5) +#define CPUID_SMX (1 << 6) +#define SGX_GLOBAL_ENABLE (1 << 18) +#define PLATFORM_INFO_SET_TDP (1 << 29) +#define IA32_BIOS_UPDT_TRIG 0x79 +#define IA32_BIOS_SIGN_ID 0x8b +#define IA32_MPERF 0xe7 +#define IA32_APERF 0xe8 +#define IA32_MCG_CAP 0x179 +#define IA32_PERF_STATUS 0x198 +#define IA32_PERF_CTL 0x199 +#define IA32_THERM_INTERRUPT 0x19b +#define IA32_MISC_ENABLE 0x1a0 +#define IA32_ENERGY_PERF_BIAS 0x1b0 +#define ENERGY_POLICY_PERFORMANCE 0 +#define ENERGY_POLICY_NORMAL 6 +#define ENERGY_POLICY_POWERSAVE 15 +#define IA32_PACKAGE_THERM_INTERRUPT 0x1b2 +#define IA32_PLATFORM_DCA_CAP 0x1f8 +#define IA32_PAT 0x277 +#define IA32_MC0_CTL 0x400 +#define IA32_MC0_STATUS 0x401 +#define IA32_PM_ENABLE 0x770 +#define IA32_HWP_CAPABILITIES 0x771 +#define IA32_HWP_REQUEST 0x774 +#define IA32_HWP_STATUS 0x777 +#define IA32_PQR_ASSOC 0xc8f +/* MSR bits 33:32 encode slot number 0-3 */ +#define IA32_PQR_ASSOC_MASK (1 << 0 | 1 << 1) +#define IA32_L3_MASK_1 0xc91 +#define IA32_L3_MASK_2 0xc92 + +#ifndef __ASSEMBLER__ #if defined(__ROMCC__) typedef __builtin_msr_t msr_t; @@ -93,5 +123,5 @@ static __always_inline void wrmsr(unsigned int index, msr_t msr) #endif /* CONFIG_SOC_SETS_MSRS */ #endif /* __ROMCC__ */ - +#endif /* __ASSEMBLER__ */ #endif /* CPU_X86_MSR_H */ -- cgit v1.2.3