From 3f8bff7764a564b839b139aabca6086f40d1a7af Mon Sep 17 00:00:00 2001 From: Kane Chen <kane.chen@intel.com> Date: Fri, 28 Jan 2022 13:58:21 +0800 Subject: soc/intel/alderlake: Add Alder Lake P IGD device IDs This patch adds additional IGD device IDs as per document 638514. BUG=b:216420554 TEST=coreboot is able to probe the IGD device during PCI enumeration. Change-Id: I0cafe92581c454da5e4aeafd7ad52f0e65370b11 Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61441 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> --- src/include/device/pci_ids.h | 3 +++ 1 file changed, 3 insertions(+) (limited to 'src/include') diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 22962c3885..6b53bb06b5 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3902,6 +3902,9 @@ #define PCI_DEVICE_ID_INTEL_ADL_P_GT2_4 0x46a8 #define PCI_DEVICE_ID_INTEL_ADL_P_GT2_5 0x46b3 #define PCI_DEVICE_ID_INTEL_ADL_P_GT2_6 0x46a6 +#define PCI_DEVICE_ID_INTEL_ADL_P_GT2_7 0x4628 +#define PCI_DEVICE_ID_INTEL_ADL_P_GT2_8 0x46b1 +#define PCI_DEVICE_ID_INTEL_ADL_P_GT2_9 0x4626 #define PCI_DEVICE_ID_INTEL_ADL_S_GT1 0x4680 #define PCI_DEVICE_ID_INTEL_ADL_M_GT1 0x46c0 #define PCI_DEVICE_ID_INTEL_ADL_M_GT2 0x46aa -- cgit v1.2.3